Tag Archives: Formal Verification

OneSpin Quantify MDV Formal Metric-driven Verification Solution

OneSpin Solutions introduced Quantify MDV, which is an enhancement to the OneSpin 360 MV product family. The Quantify MDV formal metric-driven verification (MDV) solution automatically analyzes and measures formal verification progress and quality in register transfer level (RTL) designs. Quantify MDV is available now as part of the standard 360 MV product line, which starts at $25,000 for a one-year time-based license.

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Jasper DFI Formal Verification Proof Kits for DDR-PHY Specification

Jasper Design Automation rolled out Proof Kits for the DFI (DDR-PHY) specification. The new DFI Proof Kits are currently available and provided at no additional charge to current licensees of Formal Testplanner. Other Jasper Proof Kits include AMBA 4 with AMBA 4 AXI, AXI-Stream and AXI-Lite interfaces; LPDDR1, LPDDR2, DDR, DDR2 and DDR3 SDRAM; AHB and AHB Lite; APB; Ethernet MDIO; OCP-IP; and PCI-Express.

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Vennsa Technologies OnPoint Verification Tool for Automated Debugging

Vennsa Technologies introduced OnPoint verification tool for automated debugging. OnPoint automates the manual root cause analysis performed by verification engineers once a functional failure occurs. It picks up where simulation and formal verification tools leave off by automatically analyzing the problem and pointing to the exact lines of code where the failure can be fixed. This error localization process is performed with no intervention by the engineer.

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SYSGO PikeOS Correctness Presentation at Embedded World

SYSGO will make a technical presentation on operating system correctness at Embedded World 2010 in Nuremberg. For composite systems, high levels of the Common Criteria standard make mandatory the formal verification of the OS layer(s) that interface the user application with the hardware platform. Correctness of this software component is one of the major challenges that embedded solution suppliers are increasingly facing. The presentation will focus on the methods and techniques used in the formal verification process applied to the PikeOS safe and secure virtualization RTOS platform.

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Jasper Design Automation Formal Verification Proof Kits

Jasper Design Automation rolled out Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. The new LPDDR and DDR3 Proof Kits both speed verification for these high-demand memories, and ensure conformance with industry standards. The new DDR Proof Kits are currently available as a chapter within Jasper Formal Testplanner, and provided at no additional charge to current licensees of Formal Testplanner.

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