Tag Archives: flow

Mentor Graphics Debuts Version 9.5 of PADS Desktop PCB Design Tool

Mentor Graphics PADS v9.5 desktop PCB design solution

Mentor Graphics announced version 9.5 of their PADS desktop PCB design solution. PADS enables engineers and design teams to develop PCBs within a highly productive and easy-to-use environment. PADS is ideal for schematic entry, analog design, signal and power integrity, thermal analysis, and PCB layout-to-manufacturing preparation.

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Synopsys IC Compiler 2010.03

Synopsys released IC Compiler 2010.03 physical implementation solution. IC Compiler 2010.03 offers performance improvements across the board. Early results show that IC Compiler 2010.03 is delivering more than 3X faster runtimes compared to the previous tapeout flow. IC Compiler 2010.03 is available now. It includes a quad-core license enabling multi-core processing as a standard feature.

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Calypto Design Systems PowerAdviser Flow

Calypto Design Systems introduced a new PowerAdviser Flow. The new flow enables designers to deliver power-optimized SoC designs. Using sequential design information generated by Calypto’s PowerPro CG and PowerPro MG tools, the PowerAdviser Flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power.

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CEVA Embedded Processors Webinar

CEVA will host a webinar on January 12, 2010 at 8:00 am Pacific (11:00 am Eastern / 16:00 GMT). The title of the webcast is: Optimize your Software Development Flow — An intelligent C-level development process for modern embedded processors. Overview: In the online seminar, CEVA will explore the latest challenges in software development for advanced embedded architectures and propose a practical flow to meet target performance with minimal risk and shortest development time.

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eASIC eTools 8.0 Software Suite for 45nm Nextreme-2 Designs

eASIC introduced eTools 8.0 software suite for implementing 45nm Nextreme-2 designs. The eTools 8.0 tool suite delivers a robust ASIC grade design flow with the simplicity, ease of design, and a cost point that is normally associated with FPGA design tools. By focusing on ease-of-use, and low cost of entry, eASIC is now enabling designers to make a seamless transition to adopting Nextreme-2 devices as a lower cost and lower power alternative to FPGAs and a lower NRE alternative to traditional ASICs.

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