Tag Archives: Floorplan

Synopsys Design Compiler 2010

Synopsys introduced Design Compiler 2010. The tool enables RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Design Compiler’s new scalable infrastructure tuned for multicore processors results in 2X faster synthesis runtimes on four cores. Design Compiler 2010 reduces iterations and run times in physical implementation.

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