Tag Archives: Evatronix

USB 3.0 Performance Validation Webinar

Evatronix and LeCroy will host a joint USB 3.0 webinar. The online seminar will explain step by step how the different hardware and software layers affect the data transfer speed while providing actual measures. The webinar will present the important issues engineers will face when designing their systems. The USB 3.0 Performance Validation webcast will take place on March 3rd, 2011 at 14.30 CET. The event will also be repeated on March 16th, 2011 at the same time.

Continue reading

Evatronix 65C02 Microprocessor IP Core

The Evatronix C65C02 IP core is a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology. The C65C02 is a fast 8-bit microprocessor IP that implements the same instruction set as the 65C02 microprocessor chip, which is an upgraded version of the NMOS-based MOS Technology 6502 8-bit CPU. The Evatronix C65C02 IP core is available for licensing now. The core includes synthesis and simulation support scripts for most environments, Verilog or VHDL test bench, and a reference design for the proprietary evaluation board.

Continue reading

Evatronix Technical Seminars at IP-ESC 2009

Evatronix is offering a day full of free technical seminars on December 2nd. The seminars will be held at IP-ESC 2009 (IP-Embedded Systems Conference). Their seminar topics include SuperSpeed USB 3.0, choosing NAND flash, SuperSpeed USB 3.0 IP verification, USB 3.0 mass dtorage spplication, and NAND Flash memories status. Evatronix will also showcase their USB 3.0 Device Controller in their booth.

Continue reading