Mentor Graphics introduced their unified embedded software debugging platform. The common platform enables embedded software developers to access technology data from hardware design tools without leaving their native embedded software environment. The platform integrates Mentor Embedded Sourcery CodeBench embedded software development tools with Mentor’s electronic system level, verification, and hardware emulation products.
Through a TLM-2.0 transactor adapter, EVE’s ZeBu fast emulation platforms now support the Transaction-Level Modeling Standard (TLM)-2.0, the Open SystemC Initiative (OSCI) interface standard for SystemC model interoperability and reuse. TLM-2.0 support gives software developers and hardware verification teams an interoperable way to map their SoC development environments to EVE’s emulators. It ties both ESL virtual platforms and simulation environments more closely to ZeBu and to each other, providing a standards-based methodology to reuse components for software development, hardware verification and hardware/software co-verification.
JEDA Technologies introduced the Intelligent Traffic-profile Generator (ITG). JEDA ITG is a dynamic traffic profile generator for ESL model verification. For advanced multi-core designs, ITG addresses the need for early architecture exploration when software or a particular device model is not available yet. JEDA ITG is available for Windows and Linux.
Synfora is oferring an on-demand webinar that describes the Fundamentals of ESL Synthesis. The webcast will provide RTL designers, systems engineers, and design managers with technical insight into the benefits of high level synthesis, how it operates, and the kinds of transformations that can be made. The online course is presented by Brian Bailey, who is an independent consultant working in the areas of functional verification and ESL. He provides methodology guidance and technical insights to both the EDA industry and the systems industry.
The Open SystemC Initiative (OSCI) announced that the Taiwan SystemC Users Group (TSCUG) will host a forum on November 16 (1:00-5:30 PM) at the Ambassador Hotel (188, Chung Hwa Road, Section 2, Hsinchu, Taiwan). The event is free of charge to the electronic design community. The first-ever TSCUG forum features presentations from industry experts and academia who will discuss ESL design today and best practices moving forward.