Cadence Design Systems recently introduced their PCIe Controller and PHY solution. The new design IP is ideal for low-power PCI Express (PCIe) development. The PCIe 3.0 controllers and PHY will help designers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts. The solution is ideal for datacenter and enterprise applications.
The workshop in the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications (NESEA 2011) has issued a call for papers. All accepted and presented papers in DATICS-NESEA’11 will be included in the NESEA 2011 proceeding published by IEEE. Special issues of international journals such as Journal of Internet Services and Applications (JISA), IJDATICS and IJCECS will be arranged for selected papers. The deadline for full paper submission is August 14, 2011. NESEA is sponsored by IEEE Computer Society (US) (TBC) and Distributed Thought (UK).