Tag Archives: Encounter

SMIC 40nm Reference Flow Features Cadence Encounter Digital Technology

Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.

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Cadence Releases New RTL-to-GDSII Flow for Giga-Scale, 20nm Designs

Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.

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Cadence Digital End-to-end Flow for 28nm Giga-gate/Gigahertz Designs

Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire chip flow holistically. It supports Cadence’s approach to Silicon Realization, which is a key element of the EDA360 vision. The new flow is available now.

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Cadence Encounter Digital Implementation System 9.1

Cadence Encounter Digital Implementation (EDI) System 9.1 is a digital design, implementation, and verification environment for the development of large-scale, complex SoCs. EDI System 9.1 helps designers develop low power and mixed signal SoCs at 32- and 28-nanometer with hundreds of millions of gates, including hundreds of IP elements and embedded processors.

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SMIC-Cadence 65nm Low Power Reference Flow 4.0

Cadence Design Systems introduced a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation (SMIC). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform. The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability.

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