Cadence Design Systems introduced a new SpeedBridge Adapter for PCIe 3.0. The adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The Cadence SpeedBridge Adapter for PCIe 3.0 is available now.
Mentor Graphics introduced iSolve SAS and SAS transaction-based verification IP (VIP) solution. iSolve SAS is a plug-and-play hardware interface to the Veloce family of hardware emulators. The VIP solution delivers both a simulation environment, using the Questa verification platform, and accelerated simulation environment using the Veloce hardware for the verification of SAS Gen2-compliant devices. Both solutions are available now for deployment at customer sites.
Cadence Design Systems made two announcements today. First, the company developed new in-circuit acceleration based on the Incisive and Palladium XP platforms for their System Development Suite. Cadence’s second announcement involved extensions to the Verification IP Catalog for acceleration and emulation that enable engineers to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.
Mentor Graphics introduced the Veloce2 emulation platform for the verification of electronic system and Systems on Chip (SoC) designs. Mentor also announced Veloce VirtuaLAB, which gives verification engineers access to easy-to-use, software-based peripherals, connected to the Veloce platform. Veloce2 helps software and hardware engineers verify the embedded software and SoC components of high-end CPUs, network switches/routers, digital set-top boxes, tablet PCs, netbooks, smartphones, digital cameras and other electronic products. The Veloce2 platform and Veloce VirtuaLAB are available now.
According to Mentor Graphics, their Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. The Questa Codelink with support for ARM Cortex A7, Cortex A15, other Cortex A-family, Cortex R-family, and Cortex M-family processors and Questa Verification IP with support for AMBA4 ACE are available now.
Mentor Graphics and MoreThanIP teamed together on emulation solutions for the verification of Multi-Gigabit Ethernet Systems-on-Chips (SoCs). Their solution combines Mentor Veloce hardware emulation technology and the iSolve application solutions with MoreThanIP’s Ethernet 40G/100G MAC/PCS IP Cores. Mentor Graphics is a leader in advanced system verification solutions. MoreThanIP is a leader in delivery of IP products for high-speed communications, serial backplanes, and embedded system technologies.
Mentor Graphics introduced their next-generation platform to accelerate the verification of 100-Gigabit Ethernet products. The platform features the Veloce family of emulation products and the iSolve Ethernet Switch solution. The Mentor platform enables network equipment designers to test complete systems, including software and hardware, and employ real-world network traffic early in the development cycle. The solution is available now for deployment.
Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.
AdaCore launched GNATemulator emulator solution for testing embedded software applications. GNATemulator enables software developers to compile code directly for their target architecture and run it on their host platform. The tool translates the target object code to native instructions on the host. GNATemulator is based on the QEMU technology, which is a generic and open source machine emulator and virtualizer. The AdaCore emulator is a streamlined, low-cost alternative to time-accurate target board simulators. GNATemulator is available now.
EVE has enhanced the design debugging capabilities of their ZeBu (for Zero Bugs) emulation platform. ZeBu now features Combinational Signal Access (CSA), which enables engineers to dynamically generate complete waveforms of designs. Combinational Signal Access improves productivity and lowers the cost of ownership. CSA comes as a standard component to the ZeBu family. It is available now and, initially, works with zFast, ZeBu Fast Synthesis used with ZeBu emulation systems.