Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.
Synopsys rolled out DesignWare Embedded Memory and Logic Library IP for TSMC’s 28 nanometer high-performance and high-performance for mobile process technologies. The DesignWare Embedded Memories and Logic Libraries for TSMC’s 28HP and 28HPM processes are part of the DesignWare Duet Package, which includes SRAMs, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs. The Duet Package for TSMC’s 28HP and 28HPM processes is available now.