Tag Archives: EEMBC

Mentor Graphics’ Nucleus SMP RTOS Supports Multi-threaded MIPS32 34K Core

Mentor Graphics announced the Nucleus product integration and SMP (symmetric multiprocessing) support for the MIPS32 34K core that utilizes MIPS Technologies’ MT (hardware Multi-Threading) technology. The combined technology increases embedded application performance by over 20%. In addition, it does this without increasing power consumption or silicon size. Nucleus RTOS with MIPS’ 34K core provides embedded developers with system performance gains at a much lower cost.

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Carbon Design Systems and Cadence Design Systems Team on Performance Analysis Kit

Carbon Design Systems and Cadence Design Systems announced the availability of a Carbon Performance Analysis Kit. The CPAK accelerates the intellectual property (IP) benchmark process. The Carbon/Cadence CPAK is available now from Carbon’s IP Exchange web portal. Ported CoreMark benchmarking software is available from coremark.org.

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EEMBC to Benchmark Embedded Processors with Floating Point Units

The Embedded Microprocessor Benchmark Consortium (EEMBC) is developing new benchmarks that will track the performance of embedded processors with floating-point hardware units. Floating point (FP) refers to the ability of an embedded processor to crunch numbers that are too large or small to be represented as integers. Many embedded processors include hardware FP units (FPUs) to enable higher levels of precision. The new EEMBC benchmarks will enable embedded system developers to evaluate FPU performance on the basis of consistent and controlled data.

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