Tag Archives: DSPs

IntegrIT Nature DSP Signal+ for Tensilica HiFi Audio DSP

The IntegrIT NatureDSP Math library is now available for Tensilica’s HiFi Audio DSPs for system-on-chip (SOC) design. The NatureDSP Math library simplifies the software development process for design teams that want to port software codecs to the Tensilica HiFi Audio DSP. The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for implementation of typical digital signal processing functions which efficiently utilize the HiFi Audio DSP architecture. It contains highly optimized routines for filtering, FFT, matrix, trigonometric and other math operations.

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GE Intelligent Platforms AXISLib-GPU Math and DSP Library

GE Intelligent Platforms introduced AXISLib-GPU, which is a library of optimized math and DSP functions that supports the rapid development of multiprocessing applications that take advantage of the power of GPGPU (general purpose processing on a graphics processing unit) technology. AXISLib-GPU supports the development and speeds the deployment of high performance DSP and multiprocessing applications on GE’s NVIDIA CUDA-enabled GPGPU platforms (such as the IPN250, NPN240 and GRA111). AXISLib-GPU can operate in a standalone mode or as an integral software module within the AXIS Advanced Multiprocessor Integrated Software environment.

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Texas Instruments C6EZFlo Graphical Software Development Tool

Texas Instruments (TI) announced the C6EZFlo graphical software development tool. C6Flo can be used in conjunction with TI’s Code Composer Studio IDE or other DSP-based development tools. The C6Flo EZ tool enables developers to generate prototype software on TI DSPs without learning new programming languages or specific DSP architecture. The applications can be used as-is or as prototypes to accelerate conventional C-language development. The C6EZFlo graphical software development tool is available for download free.

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Tensilica FLAC Decoder for the Xtensa HiFi Audio DSP

Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not encumbered by patents, and has an open-source reference implementation. Tensilica’s FLAC decoder supports both stereo and multi-channel formats.

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VSIDE Integrated Development Environment for VSDSP DSP Family

VLSI Solution introduced the VSIDE integrated development environment for the V16/40-bit VSDSP digital signal processor family. VSIDE offers a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, and profiler. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform.

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Tensilica ConnX 545CK 8-MAC VLIW Digital Signal Processor Core

Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die and up to 30% lower power consumption. The ConnX 545CK Revision C is available now.

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Texas Instruments TMS320C5515 Fingerprint Development Kit

Texas Instruments (TI) introduced the TMS320C5515 Fingerprint Development Kit for integrating of fingerprint biometric features into embedded systems. The C5515 Fingerprint Development Kit features a core board based on TI’s C5515 digital signal processor (DSP), two widely-used sensor types (swipe and optical), and optimized application software to ease product creation and implementation. The kit can reduce the product design cycle by 9 to 12 months. The TI TMS320C5515 fingerprint is priced at $79 USD.

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Synopsys System Studio with Matrix and Vector Data-Type Support

Synopsys introduced new capabilities for their System Studio C/C++ model-based analysis and simulation environment. System Studio now supports matrix and vector data-type, which reduces the coding and debugging effort necessary to author signal processing simulation models. In addition, System Studio integrates highly efficient parallelized matrix and vector function libraries optimized for multicore systems. The function libraries speed up simulation performance by up to eight times (8x).

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Tensilica ConnX BBE16 BaseBand Engine DSP

The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. It is a click-box configuration option with the configurable Xtensa LX3 processor core. Designers can also choose from a number of other configuration options (memories, interfaces, etc.) when designing their core. The ConnX BBE16 and an evaluation kit will be available in the second quarter of 2010.

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Tensilica HiFi EP Audio DSP IP Core

Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. The enhancements result in up to 40% lower power and up to a 50 percent size reduction.

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