Tag Archives: DRC

Cadence and GLOBALFOUNDRIES In-Design DRC+ Verification Flow

Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

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POLYTEDA One-Shot DRC Processing and Fine-Grain Physical Verification

POLYTEDA Software introduced One-Shot DRC processing and Fine-Grain Physical Verification (fgPV) for dealing with design densities and process complexities of nanoscale deep sub-wavelength process technologies. One-Shot DRC processing is different from hierarchical and traditional flat DRC processing. One-Shot takes all layers, and all rules associated with those layers, and processes them in one shot. For a given number of objects in a design, the architecture of One-Shot DRC is unique in producing predictable and almost linear runtime performance.

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OpenDFM Physical Verification Standard

The Design for Manufacturability Coalition (DFMC) have approved the first official release of the OpenDFM 1.0 standard. OpenDFM is an open, high-level DRC language that can generate verification languages with no loss of accuracy or performance. OpenDFM utilizes a more compact notation for physical verification than traditional DRC rules. Tests show OpenDFM can reduce the volume of DRC rules by 5x-20x. OpenDFM describes verification intent for leading process nodes, including conditional rules and ranges of acceptable values. It leverages a plug-in architecture to automatically generate output decks.

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Si2 OpenAccess+ Conference Registration

The Silicon Integration Initiative (Si2) will hold their annual OpenAccess+ Conference on October 20, 2010 in Santa Clara, CA. The Si2 OpenAccess+ Conference will cover the inter-related areas of OpenAccess, Design for Manufacturability (DFM), Low Power design and the newest Coalition for Open PDKs. The event will include a DFM session on the OpenDFM meta language standard, which describes DRC and DFM checks in a tool-agnostic fashion. The conference will provide updates on the industry adoption of OpenAccess and plans for the future for all coalitions.

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Synopsys Galaxy Custom Designer with SmartDRD Technology

Synopsys Galaxy Custom Designer now features SmartDRD design-rules-driven technology. SmartDRD technology enables layout engineers to more quickly achieve design-rule-check (DRC) clean designs with significantly reduced effort for analog and custom designs. SmartDRD automates many DRC repair tasks. Until now, custom layout has been primarily handled using manual methods. With SmartDRD technology, layout engineers can identify and fix DRC violations in just seconds.

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