Tag Archives: Double Patterning

Cadence Design Systems, Samsung Electronics Team on 20nm Design Methodology

Cadence Design Systems and Samsung Electronics teamed together on a 20-nanometer design methodology. Their 20nm digital design methodology features double patterning technology for joint customer deployment and internal test chips. The new design methodology enables design at 20 nanometers and future process nodes. It is ideal for mobile consumer electronics.

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KLA-Tencor PROLITH X3.1 Virtual Lithography Tool

PROLITH X3.1, from KLA-Tencor, is a comprehensive toolset that addresses advanced lithography challenges. PROLITH X3.1 virtual lithography tool helps researchers quickly and cost-effectively troubleshoot challenging issues in EUV and double patterning lithography (DPL) processes, including line edge roughness (LER) and patterning issues associated with wafer topography. With PROLITH X3.1, lithographers can streamline research, conserve valuable lithography cell resources, and accelerate product development.

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