Tag Archives: Digital Implementation

Cadence Digital Implementation and Signoff Seminar Series

The events will present the latest approaches to realizing silicon — productively and profitably. Engineers will learn about in-design signoff analysis with emphasis on timing, power, extraction, and in-design and DFM signoff at advanced nodes. Designers will also learn about the advanced technology in the latest release of Encounter Digital Implementation (EDI) System with emphasis on maximizing power savings and accelerating design closure.

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Cadence Digital Implementation and Signoff Webinars

Cadence Design Systems is offering a series of EDA360 webinars. The digital implementation and signoff webcasts will present the latest approaches to realizing silicon, productively and profitably. The first online event, Getting Back Timing Margins: Traditional OCV Alternatives, starts today at 10am Pacific time. EDA360 supports both design creators and integrators.

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Cadence Encounter Digital Implementation System 9.1

Cadence Encounter Digital Implementation (EDI) System 9.1 is a digital design, implementation, and verification environment for the development of large-scale, complex SoCs. EDI System 9.1 helps designers develop low power and mixed signal SoCs at 32- and 28-nanometer with hundreds of millions of gates, including hundreds of IP elements and embedded processors.

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