Tag Archives: DFT

Synopsys Synthesis-Based Test Technology Improves Compression by 3x

Synopsys has developed a new test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die. The new test technology is embedded in Synopsys’ Design Compiler RTL synthesis and TetraMAX ATPG solutions. Synopsys’ synthesis-based test innovation will help engineers meet more stringent test cost and quality goals within tighter design schedules.

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Real Intent Meridian DFT

Real Intent announced Meridian DFT for improving electronic design quality. Meridian DFT indentifies trouble spots during RTL creation. Meridian DFT checks the pre- and post-synthesis RTL for testability and DFT-related implementation errors. Meridian DFT will be available in Q3 2010.

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