Tag Archives: DFM

Mentor Graphics Introduces Version 9.4 of PADS PCB Design Tools

Mentor Graphics rolled out version 9.4 of their PADS PCB design tools. PADS v9.4 release provides engineers with the critical technologies required for today’s complex PCB designs. The completely integrated and scalable PADS 9.4 flow addresses high-speed, thermal, manufacturing prep, signal and power integrity, and FPGA to PCB optimizations. The PADS 9.4 software includes new associated nets functionality, which reduces design time and helps designers easily define high-speed associated nets, assign constraints, and be assured that they will be routed to those rules.

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Cadence and GLOBALFOUNDRIES In-Design DRC+ Verification Flow

Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

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OpenDFM Physical Verification Standard

The Design for Manufacturability Coalition (DFMC) have approved the first official release of the OpenDFM 1.0 standard. OpenDFM is an open, high-level DRC language that can generate verification languages with no loss of accuracy or performance. OpenDFM utilizes a more compact notation for physical verification than traditional DRC rules. Tests show OpenDFM can reduce the volume of DRC rules by 5x-20x. OpenDFM describes verification intent for leading process nodes, including conditional rules and ranges of acceptable values. It leverages a plug-in architecture to automatically generate output decks.

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Si2 OpenAccess+ Conference Registration

The Silicon Integration Initiative (Si2) will hold their annual OpenAccess+ Conference on October 20, 2010 in Santa Clara, CA. The Si2 OpenAccess+ Conference will cover the inter-related areas of OpenAccess, Design for Manufacturability (DFM), Low Power design and the newest Coalition for Open PDKs. The event will include a DFM session on the OpenDFM meta language standard, which describes DRC and DFM checks in a tool-agnostic fashion. The conference will provide updates on the industry adoption of OpenAccess and plans for the future for all coalitions.

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Webinar: Reducing Design Cost and Time With Concurrent DFM Verification

Mentor Graphics is offering a webinar titled, Reducing Design Cost and Time With Concurrent DFM Verification. The webcast will take place Jun 2, 2010 from 2:00 PM to 2:45 PM (Eastern US time). The online seminar is ideal for CAD management with time and cost objectives, NPI engineers seeking to achieve first pass manufacturability, and PCB designers trying to efficiently integrate manufacturing constraints into their design process. The webinar will be presented by Patrick McGoff of Mentor Graphics.

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Mentor Graphics vSure v9.0 DFM Tool

Mentor Graphics introduced vSure version 9.0, which is the successor to Valor Enterprise 3000 Design-for-Manufacturing (DFM) tool. vSure v9.0 enables designers to perform extensive DFM analysis during the PCB design process. This improves productivity, avoids costly design re-spins, and speeds the time to target high-volume production. The vSure product line integrates with both Mentor and non-Mentor PCB design solutions to address a worldwide market in all industry segments. The vSure release 9.0 tool is available now.

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Mentor Graphics Calibre InRoute Design and Verification Platform

Mentor Graphics introduced the Calibre InRoute design and verification platform. Calibre InRoute enables engineers to natively invoke Calibre tools within the Olympus-SoC place and route system to achieve true manufacturing closure during physical design. The Calibre InRoute automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity.

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Cadence Encounter Digital Implementation System 9.1

Cadence Encounter Digital Implementation (EDI) System 9.1 is a digital design, implementation, and verification environment for the development of large-scale, complex SoCs. EDI System 9.1 helps designers develop low power and mixed signal SoCs at 32- and 28-nanometer with hundreds of millions of gates, including hundreds of IP elements and embedded processors.

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Intel Westmere 32nm Layout and Design for Manufacturability Analysis

Chipworks announced their Design for Manufacturability (DFM) analysis of Intel’s 32 nm Clarkdale/Westmere microprocessor from the Core i5 660. The analysis combines a standard reverse engineering report with the ICWorks Surveyor format. ICWorks Surveyor is a software tool that allows the engineer to navigate thousands of images stitched together into a massive floor-plan across all the metal layers of the device. Intel Westmere 32 nm Layout and Design for Manufacturability Analysis is now shipping.

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