Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.
Synopsys introduced their new DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP. The Sonic Focus Stereo IPs enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The new Sonic Focus Stereo IP solutions are ideal for low-power DSP and cost-effective embedded stereo audio applications. The Synopsys DesignWare Sonic Focus Stereo IP solutions are available now.
A couple of announcements by Synopsys yesterday: (1) DesignWare ARC AS 221 BD dual-core processor has been optimized for high-definition (HD) audio applications and (2) three new enhancements to their DesignWare ARC 600 32-bit configurable processor family. The DesignWare AS 221 BD and the new enhancement options to the DesignWare ARC 600 family cores are available now. Synopsys’ DesignWare ARC cores enable engineers to lower integration risk and speed time-to-market for their embedded system-on-chip (SoC) designs.
Synopsys’ DesignWare STAR Memory System product family now features Self-Test and Repair Error Correcting Codes. The DesignWare STAR ECC IP is a configurable IP solution that enables designers to achieve a higher level of protection against transient errors compared to the classic ECC approach and deliver a more reliable product to the market. The DesignWare STAR ECC IP is designed to provide optimal performance of partial word writes and improved error detection/correction capability in multi-bit upsets and random bit errors.
Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.
LeCroy introduced SimPASS PE simulation design verification tool for PCI Express 3.0 protocol testing. LeCroy’s SimPASS PE provides designers with a new way to observe and analyze PCI Express-based I/O traffic. SimPASS is ideal for the pre-silicon simulation and design verification phases of development. SimPASS is based on the existing LeCroy graphical user interface for display and analysis of data traffic, and extends the data traffic analysis capabilities commonly used for post silicon testing to the simulation environment. SimPASS for PCI Express is now available.
Synopsys introduced the DesignWare High-Definition Multimedia Interface (HDMI) 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. The DesignWare HDMI IP enables designers to quickly incorporate differentiated functionality into digital TV (DTV) and home theater applications with less risk and improved time-to-market. The DesignWare HDMI 1.4 Tx and Rx IP solution is available now. The HDMI PHY IP is available in more than 10 process technologies from 90-nanometers (nm) to 40-nm, and from leading foundries.
Synopsys introduced three new DesignWare MIPI IP. The DesignWare consists of 3G DigRF Controllers and PHYs for MIPI DigRF V3 standard interface; CSI-2 Synthesizable controller for MIPI CSI-2 Host application; and D-PHY Physical Layer for MIPI CSI-2, DSI, and UniPro standard interfaces. The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller and D-PHY are available now in 65nm and 40nm process technologies.
Synopsys introduced DesignWare data converter IP solutions for 40-nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications, and video designs requiring high-performance, ultra-low power consumption and very compact area. The DesignWare Sigma-Delta ADCs, Current Steering DACs, Video DACs, and General Purpose ADCs and DACs in the 40-nm process are expected to be available in Q1 2010. The DesignWare Data Converter IP solutions are currently available in leading foundries and advanced technology processes from 180-nm to 65-nm.
Synopsys introduced DesignWare USB 2.0 picoPHY IP. The IP supports advanced 28nm processes in a 1.8V architecture, is 30% smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption. The DesignWare USB 2.0 picoPHY is ideal for mobile and high-volume consumer applications such as feature-rich smartphones, mobile internet devices, and netbooks. The DesignWare USB 2.0 picoPHY IP is expected to be available to early adopters starting in Q4 2009 for 28-nm processes, with a roadmap for 40- and 32-nm.