Synopsys introduced their new DesignWare ARC EM SEP (Safety Enhancement Package) Processor core for automotive safety-compliant applications. The ARC EM SEP core is configurable to meet the performance, power and area requirements of each target application. Giving designers the ability to define custom instructions facilitates the integration of proprietary hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required — critical requirements in embedded automotive designs.
Synopsys introduced their DesignWare HDMI 2.0 TX/RX IP solutions. The DesignWare HDMI 2.0 IP solution includes controller, PHY, and example Linux drivers. The solution reduce designers’ integration risk and time-to-market. The DesignWare HDMI 2.0 RX/TX Controller and PHY IP are available now in 28-nm process nodes from multiple foundries.
Synopsys introduced optimized Dolby MS11 Multistream Decoder for the DesignWare ARC AS211SFX and AS221BD audio processors. The MS11 Multistream Decoder is a single-package technology solution for decoding Dolby Digital Plus, Dolby Digital, and Dolby Pulse (AAC LC, HE AAC, and HE AAC v.2) audio formats. The Synopsys Dolby MS11 decoder, optimized for the AS211SFX and AS221BD audio processors, is available now.
Synopsys introduced their DesignWare Sensor IP Subsystem, which is a complete and integrated hardware and software solution for sensor control applications. The DesignWare Sensor IP Subsystem reduces integration effort and cost. The Synopsys DesignWare Sensor IP Subsystem is expected to be available in October of this year to early adopters. General availability is planned for the fourth quarter of 2013.
The Synopsys DesignWare Data Converter IP is available now in the 28-nanometer process node. The data converter IP portfolio includes DesignWare analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and integrated PLLs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems.
Synopsys has extended their DesignWare Duet Embedded Memory and Logic Library IP to enable the optimized implementation of a broad range of processor cores. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum. The DesignWare HPC Design Kit will be available for leading 28-nm processes starting in July of this year.
Synopsys introduced the DesignWare ARC EM Starter Kit for the ARC EM family of embedded processor cores. The DesignWare ARC EM Starter Kit, ARC EM4 and ARC EM6 processor cores and associated development tools are available now. The DesignWare ARC EM4 and ARC EM6 processor cores are optimized for use in embedded and deeply embedded applications such as sensors, storage devices, appliances, consumer electronics, and battery-operated devices where high performance, small size and minimal power consumption are essential.
Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.
Synopsys rolled out DesignWare Embedded Memory and Logic Library IP for TSMC’s 28 nanometer high-performance and high-performance for mobile process technologies. The DesignWare Embedded Memories and Logic Libraries for TSMC’s 28HP and 28HPM processes are part of the DesignWare Duet Package, which includes SRAMs, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs. The Duet Package for TSMC’s 28HP and 28HPM processes is available now.
According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI Express 3.0 is available now.