Tag Archives: Designs

Understanding Sampled Data Systems Webinar

Analog Devices (ADI) is offering a webinar on sampled data systems. The title of the webcast is: Understanding Sampled Data Systems – Part One. The 60-minute online seminar will take place on April 13, 2011 at 12:00 pm EST. The tutorial will focus on the conversion of analog electrical signals into digital signals, which can then be analyzed and manipulated by DSP, microcontrollers, and other embedded processors.

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Calypto PowerPro 4.1 for RTL Power Optimization

Calypto Design Systems rolled out version 4.1 of PowerPro, which is an advanced RTL power optimization product family. Calypto’s PowerPro 4.1 runs on PC platforms running Linux. PowerPro CG and PowerPro MG are each priced at $295K for a one-year, time-based license. PowerPro Analyzer is included with either PowerPro CG or PowerPro MG.

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Power Architecture Design Sessions at Linley Tech Processor Conference

Power.org will offer seven sessions at Power Architecture. The sessions will feature insights and practical design tips for engineers working with Power Architecture technology. The Linley Tech Processor Conference will take place September 27 – 28th at the Double Tree Hotel in San Jose. The event is sponsored by AppliedMicro (Premier Sponsor), Freescale and LSI, (Platinum Sponsors), and Power.org (Gold Sponsor).

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Cypress Webinar: Simplify Your Capacitive Touch-Sensing Designs

Cypress Semiconductor is offering a free webinar, entitled Simplify Your Capacitive Touch-Sensing Designs. The webcast will show designers how to create highly-integrated capacitive touch-sensing designs with programmable systems. The 60-minute online seminar will take place on Thursday, July 1 at 9:00 am PDT (16:00 Greenwich Mean Time and 12:00 PM Eastern Daylight Time).

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Introduction to Programmable Signal Chains Webinar

Cypress Semiconductor is offering an embedded design webinar titled, Introduction to Programmable Signal Chains. A programmable signal chain is a design methodology for implementing signal chains using programmable analog integrated with programmable digital logic and high-performance CPUs to provide easy-to-implement solutions to common design challenges in mixed-signal embedded design. The webcast will take place on Wednesday, June 9 at 11:00 a.m. PDT. The online seminar is 60 minutes long and is free of charge.

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Titan Analog Layout Accelerator and Titan Analog Virtual Prototyper

Magma Design Automation introduced the Titan Analog Layout Accelerator (ALX) and the Titan Analog Virtual Prototyper (AVP). Titan ALX and Titan AVP accelerate the creation and optimization of new analog design layouts, and automate the reuse of existing analog layouts in new processes and technologies. Titan ALX automatically migrates an existing analog layout to a new target technology without any DRC violations while preserving analog design intent. Titan AVP creates fast and accurate device-level prototypes and captures layout-dependent proximity effects early in the circuit design phase. Titan ALX and Titan AVP will be in production release in June 2010.

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Cadence Palladium XP Verification Computing Platform

Cadence Design Systems launched the Palladium XP verification computing platform. The solution integrates simulation, acceleration and emulation into a single verification environment. Cadence Palladium XP helps engineers design, verify, and integrate hardware and software. The Palladium XP verification computing platform is available now worldwide. It is offered in two configurations, XL for design teams, and GXL for enterprise-class global teams.

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X-FAB Analog Mixed-Signal Optimization Webinar

X-FAB Silicon Foundries will host a webinar about optimization techniques for analog mixed-signal SoC designs. The online seminar provides an overview of optimization techniques for advanced analog/mixed-signal SoC designs, showcasing X-FAB’s 0.35 micrometer foundry platform. The hour-long webcast will take place on Tuesday, April 27, 2010 at 8:30 am PDT (11:30 EDT) and 9:30 am CEST (3:30 China/Taiwan and 4:30 Korea/Japan).

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Averant Solidify 5.2

Averant introduced Solidify 5.2. The latest version of Solidify features accelerated analysis with multi-core computers, new Auto Check technology, and enhanced sequential equivalency checking (SEC). Release 5.2 is available immediately. Averant is a leader in property verification of RTL designs for digital integrated circuits.

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Tensilica HiFi EP Audio DSP IP Core

Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. The enhancements result in up to 40% lower power and up to a 50 percent size reduction.

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