Tag Archives: Designs

Cadence Design Systems Introduces SpeedBridge Adapter for PCIe 3.0

Cadence Design Systems introduced a new SpeedBridge Adapter for PCIe 3.0. The adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The Cadence SpeedBridge Adapter for PCIe 3.0 is available now.

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Mentor Graphics Debuts Questa, Veloce ARM AMBA 5 CHI and AMBA 4 ACE Tools

Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.

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Synopsys Debuts DesignWare STAR Memory System for 20nm Designs

Synopsys DesignWare STAR Memory System

Synopsys introduced the latest version of their DesignWare STAR Memory System. The tool is an automated pre- and post-silicon memory test, debug, diagnostic and repair solution. The DesignWare Star Memory System enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield. The EDA tool is available now.

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Breker TrekSoC Supports Multiple Heterogeneous Embedded Processors

Breker Verification Systems TrekSoC for SoC designs

Breker Verification Systems launched a new verion of TrekSoC for SoC designs. The Breker software now supports multiple heterogeneous embedded processors. The new verification support for multiple heterogeneous processors helps project teams verify their SoCs more completely. The latest release of TrekSoC is available to qualified verification teams now. General availability is expected at the end of 2012.

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Cadence Design Systems Publishes Mixed-Signal Methodology Guide

Mixed-Signal Methodology Guide ~ Cadence Design Systems

Cadence Design Systems announced a new publication: Mixed-Signal Methodology Guide. The design methodology book provides an overview of the design, verification and implementation methodologies required for advanced mixed-signal designs. The book addresses the complex problems facing the mixed-signal design community. It features mixed-signal design experts from Boeing, Cadence, ClioSoft and Qualcomm. The Mixed-Signal Methodology Guide is intended for chip designers and CAD engineers.

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ASSET InterTech Debuts Board Bring-up Solution for Intel Haswell Microarchitecture

ASSET InterTech announced new tools to structurally verify, functionally test, analyze performance margins and debug boards based on the Intel microarchitecture codenamed Haswell. ScanWorks board bring-up will be available in the second quarter of this year. Pricing for a base level ScanWorks platform for embedded instruments starts at $12,000.

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Mentor Graphics Releases HyperLynx v8.2 Tool Suite

Mentor Graphics rolled out HyperLynx release 8.2. HyperLynx is a suite of analysis tools for optimizing printed circuit board (PCB) designs. New features include 3D full-wave field solving, and integrated thermal/power co-simulation analysis capabilities. Specialized 3D modeling is required for analysis of multi-GHz SERDES channel interconnects (such as PCIe-Gen 3). The Mentor HyperLynx v8.2 tool suite will ship in volume next month.

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ARM and Mentor Graphics Test Flow for ARM-based Designs

Mentor Graphics and ARM teamed together on a reference flow for manufacturing test of ARM processor-based designs. The reference flow features documentation, seamless interfaces, and scripts for accelerating the development of a complete test solution for ARM IP based on the Mentor Graphics Tessent test tools. The test flow is optimized for high test quality, lower test cost and shortened design-for-test development schedules.

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Kontron COM Express Starterkit Type 6

Kontron introduced their COM Express Starterkit Type 6. The kit features an Evaluation Board that provides an easy plug-in of COM Express modules and line-up many connectors and jacks. The starterkit also includes PSU, USB stick, cables and documentation. The Kontron starterkit helps application developers develop and evaluate new systems based on the latest COM Express pin-out Type 6 Computer-on-Modules. Samples of the Kontron COM Express Starterkit Type 6 are available now. Series production is scheduled for August.

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Apache Design Solutions Offers Low-power Webinars

Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.

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