Synopsys’ unified mixed-signal IC design solution has been qualified for TowerJazz’s power management analog/mixed-signal reference design flow (Reference Flow 2.0) and 180-nanometer (nm) Power Management (PM) interoperable process design kit (iPDK). Synopsys’ tool suite, the foundry iPDK and reference design flow are verified to seamlessly work together to enable designers to quickly become productive.
Apache Design announced four online seminars for this month. The webcasts will cover simulation software platforms and methodologies that meet integrated circuit (IC) power, performance and price demands for low-power mobile, high-performance computing, consumer and automotive electronics. The Apache Low Power Webinar Series will take place July 24, July 25, July 26, and July 31.
Newark element14 and Freescale Semiconductor are hosting a webinar next week. The webcast will cover the features of the high performance, ultra low power Kinetis K and L Series microcontrollers. The event will also discuss Freescale’s range of design tools, including Code Warrior, Processor Expert, Tower System and MQX. The title of the webinar is How to Leverage Kinetis ARM solutions in your design. The online seminar will take place on Wednesday, July 18, 2012 at 12 noon CST.
Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.
Microsemi and Avnet Memec are offering a series of free technical seminars. The sessions will train engineers on the Microsemi MPM 4.0 power management solution. The technical seminars provide designers with a well-rounded experience and fast, accessible content that will have a dramatic impact on designs. The Microsemi Power Management seminars will take place in multiple locations throughout the U.S.
element14 is hosting a webinar tomorrow. The webcast will present a step-by-step guide to debugging an ARM based design with the Keil ULINK-ME debug adapter. Attendees of the webcast will also be invited to apply to RoadTest the Keil ULINK-ME, bundled with an ARM Cortex-M processor-based STM32 series development kit. element14′s RoadTest Group enables developers to test and review new products, and post their results and findings on the element14 Community. The online seminar is a part of their Design Flow Series webinar series. The free event will take place on June 19, 2012, at 10 am EST (16:00 CET).
Synopsys launched version 7.3 of their LightTools illumination design and analysis software. LightTools 7.3 includes software enhancements to help designers jumpstart, analyze, optimize and manage illumination designs. The tool includes a variety of new illumination design features in areas such as application-specific design, color quality analysis, LED phosphor modeling, and design management and performance. LightTools v7.3 is available now.
TSMC has given Phase I Certification to Synopsys design implementation tools for TSMC’s 20nm process. Synopsys’ Galaxy Implementation Platform features comprehensive support for TSMC’s latest set of 20-nm design rules. The certified tools from TSMC’s Open Innovation Platform and its ecosystem members help engineers create products that meet aggressive power, performance and area targets.
Triad Semiconductor and Mentor Graphics introduced ViaDesigner, which is a new electronic design automation (EDA) tool that enables system-level engineers, who have no previous IC design experience, to design their own mixed-signal configurable ASICs. The new approach to low cost, mixed-signal IC design enables new IC development in two to six months, allows respins in less than four weeks, and can reduce the cost and risk typically associated with custom mixed-signal IC design.
Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.