Synopsys recently launched Formality Ultra, which is a new configuration of the Formality equivalency checking solution. Formality Ultra enables designers to reduce the time and effort required to implement ECOs. This increases schedule predictability and helps engineers close designs on time. The Synopsys tool gives designers the ability to implement more complex functional changes as engineering change orders rather than wait for the next derivative of the design.
Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.
Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.