XJTAG will hold a free boundary scan training workshop at the UK’s Manufacturing Technology Centre (MTC). The workshop will provide an introduction to boundary scan and to show how the debug, test and programming process can be used throughout the product life cycle. The XJTAG workshop will take place Wednesday, June 12, 2013 in Coventry.
Synopsys introduced the latest version of their DesignWare STAR Memory System. The tool is an automated pre- and post-silicon memory test, debug, diagnostic and repair solution. The DesignWare Star Memory System enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield. The EDA tool is available now.
Synopsys has added a Performance Checker capability to their next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol. The Performance Checker capability in the Synopsys Discovery VIP helps improve the productivity of engineering teams using the AMBA protocols to meet their SoC performance goals.
Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.
Atollic introduced TrueSTUDIO for ARM v3.2. The integrated development environment for embedded microcontroller designs now offers RTOS-aware debug support for real-time operating systems like FreeRTOS, OpenRTOS, ThreadX and embOS. The ARM development tool is an integrated C/C++ solution with features for multicore debugging, improved code quality, team collaboration and increased developer efficiency. Atollic TrueSTUDIO v3.2 helps engineers to quickly develop embedded systems with higher quality and at lower cost.
Synopsys and Renesas teamed together to developed Virtualizer Development Kits. The VDKs for Renesas’ RH850 MCUs are software development tools that integrating functional models of digital hardware. The VDKs help engineers speed software development and system testing for Renesas RH850-based designs. The new VDKs for Renesas’ RH850 MCUs will be available from Synopsys in the fourth quarter of this year.
Synopsys released version 12.06 of their Virtualizer tool set for creating virtual prototypes and Virtualizer Development Kits (VDKs) for accelerating embedded software development. Virtualizer 12.06 release makes it easier for design teams to create virtual prototypes and deploy them to software engineers in VDKs. The new Virtualizer 12.06 release is available now.
EVE introduced e-zTest 10GbE, which is a 10-Gigabit Ethernet validation platform for their ZeBu (Zero Bugs) family of system-on-chip (SoC) hardware-assisted verification platforms. The e-zTest 10GbE software is a transaction-based environment for high-speed validation of 10GbE functions in network routers, switches and controllers, and SoC application specific integrated circuits (ASICs) containing 10GbE ports.
ASSET InterTech announced new tools to structurally verify, functionally test, analyze performance margins and debug boards based on the Intel microarchitecture codenamed Haswell. ScanWorks board bring-up will be available in the second quarter of this year. Pricing for a base level ScanWorks platform for embedded instruments starts at $12,000.
OnPoint, from Vennsa Technologies, now features causality analysis analysis and failure triage engines. The causality analysis engine can determine the root cause of failures at a fine resolution and with high accuracy. The triage engine automatically screens failures and generates an X-ray picture of what is going on in the design and where the error source is originating from. OnPoint diagnose and triage engines are available now and can be purchased separately using time-based licenses.