Jasper Design Automation announced Intelligent Proof Kits for accelerated certification of advanced SoC interconnect protocols. Jasper Intelligent Proof Kits ship unencrypted with original source code to facilitate user customization and insights into the protocols themselves. Jasper is initially releasing Intelligent Proof Kits for AMBA 3 and AMBA 4. DFI, DDR and LPDDR versions will roll out a little later.
Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.