The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of over 1 GHz in 45 nm process technology (45GS) with an area of just 0.044 mm2. The configurable and extensible Xtensa LX4 DPU is available now. The IP core is ideal for handling complex compute-intensive DSP applications where an RTL implementation may be the only other option.
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.