A couple of announcements by Synopsys yesterday: (1) DesignWare ARC AS 221 BD dual-core processor has been optimized for high-definition (HD) audio applications and (2) three new enhancements to their DesignWare ARC 600 32-bit configurable processor family. The DesignWare AS 221 BD and the new enhancement options to the DesignWare ARC 600 family cores are available now. Synopsys’ DesignWare ARC cores enable engineers to lower integration risk and speed time-to-market for their embedded system-on-chip (SoC) designs.
Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.
Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock speed, up to 20% smaller die area and up to 15% less power consumption. The Diamond Standard processors are available now.
CEVA launched the Application Optimizer, which is an integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox Software Development Environment, the Application Optimizer enables application developers to easily develop software for CEVA’s DSPs purely in C-Level, eliminating any hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs.
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.