ASSET InterTech has published an introductory tutorial on IJTAG. The tutorial explains how the new IEEE P1687 Internal JTAG (IJTAG) standard simplifies and automates the way chip designers manage embedded instruments that perform chip validation and characterization. The article describes the on-chip IJTAG architecture and the two languages defined by the standard, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the connections among embedded on-chip instruments and PDL is an extension of the Tcl (Tool Command Language) for developing validation, test and debug vectors for execution by IJTAG instruments.
Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.
Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.
Imec and Holst Centre have developed integrated sensing elements for gas detection. The polymer-coated microbridges in high-density arrays can detect ppm-level concentrations of vapors using on-chip integrated read-out techniques. Thanks to the low power consumption (<1 mW/bridge) and small form factor, the technology is ideal for the miniaturization of electronic nose devices.
Dongbu HiTek will host a webinar on power management and control. The webcast is titled, New Analog and BCD Technology Releases. The webinar will discuss the latest advances in Analog CMOS and BCDMOS chip design/processing technologies and how they can be applied to perform more efficient and smarter power control and management. The online seminar will take place April 21, 2010 at 12:00 PM PDT (3:00 PM EDT) and (replay starts April 22, 2010).
Imec and Altos Design Automation will to set up a library re-characterization service based on Altos characterization tools. imec will extend their ASIC (application-specific integrated circuit) prototyping and volume fabrication service with library re-characterization, which is essential when designing in 65nm and 40nm nodes.
Apache Design Solutions announced a workshop at DesignCon 2010 to facilitate industry-wide discussion on the challenges, methodologies, and techniques required for chip-package-systems (CPS) convergence. The workshop, entitled “Practical Methodologies for Power/Signal Integrity of Chip-Package-Board Designs,” will be held from 9am to noon on Thursday, February 4th in the Santa Clara Convention Center.
IMEC announced a microchip with microscopic nail structures that enable close communication between the electronics and biological cells. The new chip is a mass-producible, easy-to-use tool in electrophysiology research (such as fundamental research on the functioning and dysfunctioning of the brain). Each micronail structure serves as a close contact-point for one cell, and contains an electrode that can very accurately record and trigger in real-time the electrical activity of an individual electrogenic cell in a network.