Tag Archives: chip-level

Apache Design Sponsors Two DesignCon Chip Package System Workshops

Apache Design, Inc. is sponsoring two Chip-Package-System (CPS) workshops at DesignCon 2012. The two in-depth technical workshops will provide designers with an open forum for exchanging the latest ideas and information on the most current technologies. In the interactive workshops, leading semiconductor companies and system houses will share perspectives and best practices on chip and package modeling, and system-level verification for signal integrity, power integrity, electromagnetic interference and thermal. The workshops are free. However, seating is limited and registration is required.

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SpringSoft Laker Blitz Chip-level Layout Editor

SpringSoft introduced the Laker Blitz chip-level layout editor. The new software tool is optimized for speed and productivity during the final steps of the physical design process. It streamlines tapeout-to-manufacturing operations by enabling high-speed viewing and editing of chip-level layouts. Laker Blitz is ideal for designs with large data sets, such as advanced-node system-on-chip (SoC) implementations and large memory chips that are widely used in consumer electronics. The new SpringSoft software is available now for production use.

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