Cadence Design Systems announced their Virtuoso Layout Suite for Electrically Aware Design (EAD). The tool for automating custom design enables layout designers and circuit designers to work together more efficiently and effectively through greater real-time visibility into electrical issues. Cadence Virtuoso Layout Suite EAD helps engineers to reduce circuit design cycle by up to 30% while optimizing chip size and performance.
Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.
This year’s ARM TechCon event will feature two technical conferences: Chip Design, and Software and Systems Design. Chip Design Day (October 25) is a one-day intensive conference for chip design teams working with ARM silicon IP and tools. Software and Systems Design Days (October 26-27) will cover all of the hardware and software, tools, ranging from low-power design, networking and connectivity to Android and open source software to safety and security. ARM TechCon will take place in Santa Clara, California.