Tag Archives: Cadence

EMA, AEi Systems announce expanded Power IC Model Library for Cadence PSpice simulator

EMA Design Automation (EMA) and AEi Systems have announced the latest version, 4.1, of the AEi Systems’ Power IC Model Library for the Cadence PSpice simulator. “This update to the power IC model library will make it easier for our PSpice customers to obtain high quality bench tested models,” says Manny Marcano, President and CEO of EMA.

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Carbon SoCDesigner Plus Features More Swap & Play Models

Carbon Design Systems recently released the latest version of SoCDesigner Plus. The new version expands the models eligible to be used with Swap & Play. SoCDesigner Plus automatically supports all fabric and DDRx memory controller components. As a result, many more design teams can boot an operating system in seconds and then debug with 100% accuracy using Swap & Play. Carbon’s newly enhanced Swap & Play support and updated CPAKs are available now for all SoCDesigner Plus users.

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Gates-on-the-Fly Fixes Logic Equivalence Check Failures White Paper

SynaptiCAD recently published a white paper that describes how their updated Gates-on-the-Fly (GOF) was used to find and fix failures identified by Cadence’s Conformal tool. SynaptiCAD’s Verilog netlist editor was updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. Gates-on-the-Fly graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool.

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Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.

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SMIC-Cadence 65nm Low Power Reference Flow 4.0

Cadence Design Systems introduced a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation (SMIC). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform. The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability.

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