Cadence Design Systems has issued a call for papers to be presented at MemCon 2013. Cadence is seeking presentations and papers on topics that illustrate users’ knowledge and expertise in memory design and architecture. The deadline for paper abstract submission is May 30, 2013. The MemCon conference showcases the thought leaders driving advances in memory technology. The event will take place August 6, 2013 at the Santa Clara Convention Center.
Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.
Cadence Design Systems released version 13.1 of the Incisive Enterprise Simulator. The latest release of the software tool improves low-power verification productivity of complex SoCs by 30%. Cadence Incisive Enterprise Simulator v13.1 features new capabilities that ease the challenge of verifying all of today’s power-aware designs.
Cadence Design Systems announced a new Mobile PCI Express design IP (IP) and verification IP (VIP) solution. According to Cadence, the solution is the first IP and VIP to support the new M-PCIe specification. Mobile PCI Express enables engineers to develop products with both PC-class performance and extended battery life.
Cadence Design Systems will hold their CDNLive Silicon Valley User Conference on March 12 and 13 in Santa Clara. CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Cadence Design Systems introduced Virtuoso Advanced Node, which is a set of custom/analog capabilities designed for the advanced technology nodes of 20 nanometers and below. Virtuoso Advanced Node enables design teams to optimize designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.
Cadence Design Systems released version 12.2 of their Incisive functional verification platform and methodologies. Cadence Incisive v12.2 provides the productivity improvements the engineering teams need to bring their designs to market fast and at high quality. The tool features a broad set of new and enhanced capabilities that double the productivity of SoC verification over the previous version.
Cadence Design Systems introduced the industry’s first Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The new IP and VIP offering helps engineer to easily implement the latest automotive requirements and create advanced Ethernet-based products for in-vehicle communication. Cadence’s Design and Verification IP enables the development of Ethernet-based products for in-vehicle communication.
Texas Instruments introduced WEBENCH Schematic Export. The software is a new online tool for exporting analog designs from TI’s WEBENCH Design Center to computer-aided design (CAD) development platforms from Cadence Design Systems, Mentor Graphics and Altium. With WEBENCH Schematic Export, engineers no longer need to manually enter the design into the CAD platform.
Cadence Design Systems released version 16.6 of their Allegro Package Designer and System-in-Package (SiP) Layout solution. Allegro now enables engineers to analyze and validate high-performance, low-power devices for electrical compliance. This improves design time and speeds time to market. New enhancements in Cadence Allegro enable a more predictable and efficient design cycle. Cadence Allegro release 16.6 IC package solution is expected to be available in the fourth quarter of this year.