Cadence Design Systems announced a suite of ultra-fast, low-power analog intellectual property (IP) products. The new data converter family includes 7-bit 3GSPS dual ADC and DAC, 11-bit 1.5GSPS dual ADC, and 12-bit 2GSPS dual DAC. The converters are ideal for designers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60 GHz spectrum with potential data throughput up to 7Gbps, as well as LTE and LTE Advanced. The Cadence 28nm Data Convertor IP family is available now.
Cadence Design Systems launched the Spectre XPS (eXtensive Partitioning Simulator). The high-performance FastSPICE simulator delivers faster and more comprehensive simulation for large, complex chip designs. The Spectre XPS FastSPICE simulator features next generation algorithms that deliver the simulation accuracy and performance required to reduce the risks of developing cutting-edge differentiated designs.
Cadence Design Systems is holding their Mixed-Signal Summit next week. The event will give attendees the opportunity to learn from experts at Cadence and other leading companies about the latest mixed signal design methodologies, and new Cadence technologies such as support for System Verilog real number modeling based on the IEEE P1800 standard. The free day-long event will take place at its San Jose headquarters on October 10th.
Cadence Design Systems introduced the Secure Digital (SD) 4.0 Host Controller Intellectual Property core. The IP core helps designers achieve the maximum memory card access performance of up to 312MB/s (three times the performance of the previous specification). The Secure Digital 4.0 Host Controller IP core is available now.
Cadence Design Systems has developed the industry’s first verification IP that supports the new HDMI 2.0 specification. The HDMI 2.0 VIP enables a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, engineers can focus on other tasks crucial to project completion.
Cadence Design Systems announced the Palladium XP II Verification Computing Platform. The tool speeds up hardware and software verification by up to 50% and extends capacity to 2.3 billion gates. Palladium XP II Verification Computing Platform is part of an enhanced System Development Suite.
Cadence Design Systems released new verification IP (VIP) models for the latest memory standards: LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM. LPDDR4 and Wide I/O 2 are key new standards for memory interfaces, and the availability of memory models will help designers to take advantage of the new standards quickly.
Cadence Design Systems introduced a new SpeedBridge Adapter for PCIe 3.0. The adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The Cadence SpeedBridge Adapter for PCIe 3.0 is available now.
Cadence Design Systems announced their Virtuoso Layout Suite for Electrically Aware Design (EAD). The tool for automating custom design enables layout designers and circuit designers to work together more efficiently and effectively through greater real-time visibility into electrical issues. Cadence Virtuoso Layout Suite EAD helps engineers to reduce circuit design cycle by up to 30% while optimizing chip size and performance.
Cadence Design Systems recently introduced their PCIe Controller and PHY solution. The new design IP is ideal for low-power PCI Express (PCIe) development. The PCIe 3.0 controllers and PHY will help designers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts. The solution is ideal for datacenter and enterprise applications.