Tag Archives: Berkeley Design Automation

Tanner HiPer Silicon v15.23 Features HiPer Simulation AFS and T-AFS

Tanner EDA's S-Edit design environment for schematic capture

Tanner EDA introduced the latest version of HiPer Silicon full-flow analog and mixed-signal design suite. HiPer Silicon v15.23 includes HiPer Simulation AFS and Tanner Analog FastSPICE (T-AFS), which integrates the Berkeley Design Automation Analog FastSPICE Platform with Tanner EDA’s S-Edit schematic capture and W-Edit waveform analyzer.

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Tanner Analog FastSPICE Features Berkeley Design Automation AFS

Tanner EDA introduced Tanner Analog FastSPICE (T-AFS), which adds Berkeley Design Automation Analog FastSPICE Platform to Tanner EDA’s full-flow HiPer Silicon design suite. With the availability of Analog FastSPICE as an add-on to Tanner EDA’s analog and mixed-signal design tools, RF designers can realize the benefits of Tanner EDA’s full-flow analog design suite. Analog FastSPICE enables verification of very complex analog/ RF circuits with nanometer SPICE-accurate results.

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2011 Nanometer Circuit Verification Forum

The 2011 Nanometer Circuit Verification Forum will take place on September 22, 2011 in Santa Clara, California. The nanometer forum will present successful approaches to verifying analog, mixed-signal, and RF circuits implemented in 90nm to 28nm silicon. The all-day event is free, but registration is required. The Nanometer Circuit Verification Forum is hosted by Berkeley Design Automation. Other EDA companies supporting the event include Accelicon Technologies, Ciranova, Invarian, MunEDA, and Solido Design Automation.

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2011 Nanometer Circuit Verification Forum

Berkeley Design Automation is hosting a forum, the 2011 Nanometer Circuit Verification Forum. The daylong event will cover data converters, PLLs and timing circuits, high-speed I/O, wireless transceivers, and image sensors. The Nanometer Circuit Verification Forum will feature technical presentations from analog and RF circuit designers from the semiconductor industry, silicon IP companies, and international universities. The event will take place September 22, 2011 in Santa Clara, California.

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Nanometer IC Variation Analysis Design Flow

Berkeley Design Automatio and Solido Design Automation teamm on a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. In the solution, Variation Designer utilizes the AFS Platform. The result is variation analysis capabilities that enable designers to rapidly reduce variation risk.

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Berkeley Design Automation Analog FastSPICE RF

Berkeley Design Automation introduced Analog FastSPICE RF (AFS RF), which is the first true SPICE accurate device noise analysis for RF circuits. AFS RF accurately analyzes nanometer-scale device noise impact for all types of pre-layout and post-layout circuits, ensuring early insight into its impact on performance, power, and area. For complex circuits, Analog FastSPICE RF is 5 to 10 times faster than traditional RF tools that can only approximate device noise effects. It is available immediately.

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