Tag Archives: Avionics

Seminar: Invoking DO-178C and Getting Ready for DO-254A

LDRA is offering a two-day seminar on DO-178C and DO-254A. The event will focus on the invocation of DO-178C and the new FAA and EASA guidance that has formed the foundation of the proposed DO-254A standard. The seminar will also explain the DO-178C processes and show how to apply them across the development lifecycle. The title of the seminar is Invoking DO-178C and Getting Ready for DO-254A.

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Extreme Engineering Solutions Avionics Development Platform

Extreme Engineering Solutions (X-ES) announced their Avionics Development Platform (ADP) for the development and rapid deployment of avionics systems. The ADP is a prepackaged 3U OpenVPX development platform that provides functionality and I/O commonly required by avionics applications. The ADP enables the deployed system hardware to be developed in parallel with the software development effort to reduce overall development schedule and risk. The Avionics Development Platform uses an OpenVPX development chassis that supports conduction-cooled payload modules, an OpenVPX backplane, and air-cooled RTMs. The same conduction-cooled 3U VPX modules used in the lab development platform can be utilized in the deployed system.

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Safety-Critical Software Reuse for Multi-Core Avionics Systems Webinar

DDC-I will host a webinar on about safety-critical software reuse for next-generation avionics and multi-core systems. The webcas is ideal for systems engineers, software engineers, and engineering managers who need to reuse software and adapt it to new target environments without changing the software. The online seminar will take place 2:00 PM EDT on May 12, 2010.

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Aldec ALINT 2009.10 for Design Rule Checking

Aldec introduced ALINT 2009.10 Design Rule Checking application. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT is Design Rule Checking software for fast design closure. ALINT analyzes and detects issues early in the design and verification cycle, and checks HDL source code of complex ASIC, FPGA, and SOC designs. It detects such problems as poor coding styles, improper clock and reset management, simulation and synthesis problems, poor testability, and source code issues throughout the design flow.

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