Tag Archives: Atrenta

Fast Track Your SoC Design Seminars

Atrenta will be holding a series of seminars. The Fast Track Your SoC Design seminars will feature new solutions and methodologies to accelerate quality IP selection, IP integration and SoC assembly, and successful RTL hand-off. The Atrenta seminars will take place in Ottawa, Canada (September 13); Austin, TX (September 20); Santa Clara, CA (September 27); and Bangalore, India (October 13). Additional locations will be scheduled at a later date.

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Atrenta SpyGlass v4.5

Atrenta launched version 4.5 of their SpyGlass product family. SpyGlass 4.5 features improvements in usability, debug, advanced linting, power estimation and reduction, CDC verification, constraints management, and testability. SpyGlass v4.5 is now in production and available for download. Atrenta’s SpyGlass solution methodology provides a structured, easy to use and a comprehensive method for solving RTL design issues.

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Atrenta SpyGlass-Physical for Early Implementation Analysis

Atrenta launched SpyGlass-Physical tool for early implementation analysis. SpyGlass-Physical provides early estimates of area, power, timing and routability for RTL designers without the need for physical design expertise or tools. The tool helps to achieve performance targets in concurrent block/SoC development processes by using interactive implementation analysis features. The result is enhanced guidance for the actual implementation of both IPs and full-chip SoCs. SpyGlass-Physical is currently in limited deployment.

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A Power Backbone for Architecture to RTL Power Efficient SoC Design

Bernard Murphy, Chief Technology Officer of Atrenta, will present a paper at ARM techcon3 (formerly ARM Developers Conference) from 10:00 to 10:45 am on Friday, October 23, 2009. The title of the paper is A Power Backbone for architecture to RTL power efficient SoC Design. Dr. Murphy’s paper describes a real-world implementation of such an RTL-based design flow.

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