Cortus announced their APS5 embedded microcontroller. The Cortus APS5 is a 32-bit general purpose CPU. The processor IP is designed for demanding embedded systems. It features a high performance integer unit and an instruction cache. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.
Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.
Triad Semiconductor and Mentor Graphics introduced ViaDesigner, which is a new electronic design automation (EDA) tool that enables system-level engineers, who have no previous IC design experience, to design their own mixed-signal configurable ASICs. The new approach to low cost, mixed-signal IC design enables new IC development in two to six months, allows respins in less than four weeks, and can reduce the cost and risk typically associated with custom mixed-signal IC design.
Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.
EVE launched the ZeBu-Blade2 hardware-assisted verification platform. ZeBu-Blade2 is an emulator for application specific integrated circuits (ASICs) and systems on chip (SoCs) implemented in 40-nanometer (nm) technology. It is the first member of the ZeBu emulation family based on Xilinx Virtex6-LX760 field programmable gate arrays (FPGAs). ZeBu-Blade2 is available now. It includes its zFAST, fast synthesis, and a set of ZeBu transactors.
Cadence Design Systems introduced over 600 new capabilities to improve verification productivity for ASIC and FPGA designers. The capabilities, along with support for the Accellera Universal Verification Methodology (UVM), will expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.
TotalHistory, from GiDEL, is a software only solution that enables engineers to have visibility of any signal in their designs, for virtually unlimited trace depth, with no or minimal degradation in performance. TotalHistory is available with GiDEL’s PROC_SoC ASIC Prototyping Systems and PROC Boards FPGA-based High Performance Computing (HPC) accelerators.
eASIC rolled out eTools 8.1 Design Suite for 45nm Nextreme-2 designs. The eTools 8.1 based design flow helps designers to simply perform front-end design conversion and back-end implementation. New features and enhancements in eTools 8.1 enable designers to reduce overall design time by up to 40% while increasing design performance by up to 30% compared to the previous eTools 8.0 suite. FPGA and ASIC designers can try a 30-day evaluation of eTools 8.1 for free.
Synopsys announced the HAPS-60 series of ASIC rapid prototyping systems for complex SoC design and verification. The HAPS-60 series is an easy-to-use and cost-effective rapid prototyping system that enables early hardware/software co-verification and system-level integration at near-real-time run-rates, using at-speed, real-world interfaces. The HAPS-60 series is built with Xilinx Virtex-6 devices.
Imec and Altos Design Automation will to set up a library re-characterization service based on Altos characterization tools. imec will extend their ASIC (application-specific integrated circuit) prototyping and volume fabrication service with library re-characterization, which is essential when designing in 65nm and 40nm nodes.