Tag Archives: Ascent Lint

Real Intent Ascent Lint 1.4

Real Intent released version 1.4 of Ascent Lint solution for performing syntax and semantic lint checks for complex SoC designs. Ascent Lint 1.4 includes new features to improve design productivity and the comprehensiveness of rule checking. These features incremental reporting, scope-based analysis, and enhanced waiver capabilities. Real Intent Ascent Lint 1.4 is available now.

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Real Intent Ascent Lint v1.3

Real Intent rolled out version 1.3 of Ascent Lint. The new version adds VHDL checks to its existing Verilog checks. It is a tool that performs syntax and semantic Hardware Description Language (HDL) lint checks for complex SoC designs. Ascent Lint features a fast engine and low noise report for debugging electronic designs. Ascent Lint 1.3 is available now.

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Real Intent Ascent Lint v1.2

Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.

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