Tag Archives: Apache Design

ANSYS and Apache Offer Dimensions of Electronic Design Seminars

ANSYS Dimensions of Electronic Design Seminar

ANSYS and Apache Design announced a series of free seminars about simulation software platforms and methodologies that meet integrated circuit (IC) power, performance and price demands for low-power mobile, high-performance computing, consumer and automotive electronics. The events will take place in Boston, Massachusetts; Santa Clara and Los Angeles, California; Austin, Texas.

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Apache to Host Low Power Webinar Series

Apache Design announced four online seminars for this month. The webcasts will cover simulation software platforms and methodologies that meet integrated circuit (IC) power, performance and price demands for low-power mobile, high-performance computing, consumer and automotive electronics. The Apache Low Power Webinar Series will take place July 24, July 25, July 26, and July 31.

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ANSYS Introduces RedHawk-3DX 20nm Power Sign-off Solution

RedHawk-3DX GUI showing multiple die with silicon interposer

ANSYS launched RedHawk-3DX, which is a fourth-generation power sign-off solution. RedHawk-3DX is designed to meet the power, performance and price demands of low-power mobile, high-performance computing, consumer and automotive electronics. RedHawk-3DX extends previous generations’ capabilities to address sub-20 nanometer (nm) designs with 3+ gigahertz performance and billions of gates. It is also architected to support the simulation of emerging chip and packaging technologies using multi-die three-dimensional ICs (3D-ICs) for smart electronic products.

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Apache Design Sponsors Two DesignCon Chip Package System Workshops

Apache Design, Inc. is sponsoring two Chip-Package-System (CPS) workshops at DesignCon 2012. The two in-depth technical workshops will provide designers with an open forum for exchanging the latest ideas and information on the most current technologies. In the interactive workshops, leading semiconductor companies and system houses will share perspectives and best practices on chip and package modeling, and system-level verification for signal integrity, power integrity, electromagnetic interference and thermal. The workshops are free. However, seating is limited and registration is required.

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