Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.
This year’s DATE 2011 conference will feature two educational technical workshops hosted by Apache Design Solutions. The Chip-Package-System Methodology from Early Stage to Sign-off workshop will take place on March 15th. The Power Methodology for Energy Efficient Designs workshop will take place March 16th. Apache Design Solutions will also present two technical papers at DATE: Ball Grid Array Packages Electrical Optimization Using Apache Package Modeling Tools and System Level Power Integrity Analysis and Supply Network Optimization of a Dual Core CPU.
At the Microelectronics Packaging and Test Engineering Council (MEPTEC) Technical Symposium, Apache Design Solutions will take part in a technical session, Co-Design Solutions – Bridging the Gap from Silicon to System. The session will focus on fast 3D EM simulations. MEPTEC takes place in San Jose, California, on Thursday, February 25.
Apache Design Solutions announced a workshop at DesignCon 2010 to facilitate industry-wide discussion on the challenges, methodologies, and techniques required for chip-package-systems (CPS) convergence. The workshop, entitled “Practical Methodologies for Power/Signal Integrity of Chip-Package-Board Designs,” will be held from 9am to noon on Thursday, February 4th in the Santa Clara Convention Center.
Apache Design Solutions will hold three Apache Technology Forums in Asia in November 2009. Seminars in Japan, Korea, and Taiwan will feature presentations by Apache’s customers on methodologies and best practices for addressing chip-package-system (CPS) challenges and Apache’s power and noise solutions for making CPS convergence a reality.