Tag Archives: Analog

Design Conference 2013 Features 16 Technical Sessions

Analog Devices, Xilinx, and MathWorks announced a series of design conferences for analog, mixed-signal and embedded systems engineers. During the conference, attendees will learn how MATLAB and Simulink can be used to develop, model and deploy high-performance signal processing systems. Design Conference 2013 will take place in the United States, Germany and China. Avnet, Digilent and 4DSP, sponsors of the U.S. conferences, will showcase their industry-leading solutions based on ADI’s analog and mixed-signal technologies.

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ProPlus Design Solutions Debuts NanoYield Design for Yield Software

ProPlus Design Solutions launched NanoYield design for yield software. It is a fast and accurate yield prediction and optimization tool for memory, logic, analog and digital circuit design. The toolset is faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis. NanoYield is part of ProPlus Design Solutions’ transistor-level statistical modeling and design and variations-aware product portfolio. It is shipping now.

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Synopsys DesignWare IP Available for SMIC 40-nanometer Low-Leakage Process

Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

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ADI Webinar: Demystifying the JESD204B High-speed Data Converter-to-FPGA Interface

Analog Devices will host a free webinar about the JESD204B standard. The online seminar will take place Wednesday, April 18, 2012 at 12:00 pm EDT. The title of the webcast is Demystifying the JESD204B High-speed Data Converter-to-FPGA Interface. The ADI webcast is ideal for engineers designing within the FPGA/analog signal chain system ecosystem.

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2011 Nanometer Circuit Verification Forum

Berkeley Design Automation is hosting a forum, the 2011 Nanometer Circuit Verification Forum. The daylong event will cover data converters, PLLs and timing circuits, high-speed I/O, wireless transceivers, and image sensors. The Nanometer Circuit Verification Forum will feature technical presentations from analog and RF circuit designers from the semiconductor industry, silicon IP companies, and international universities. The event will take place September 22, 2011 in Santa Clara, California.

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Tanner EDA to Host Three Webinars

Tanner EDA announced three webcasts for April. The HiPer Verify webinar will take place April 5th and will explain how to the HiPer Verify DRC/ LVS tool to run verification throughout the design cycle to ensure error-free and timely tapeouts. The L-Edit webinar will take place on April 14th and show how to use L-Edit to reduce the unpredictable costs and workload related to a tapeout deadline. The HiPer DevGen webinar will take place April 21st and will demonstrate how to reduce weeks of design time into minutes for current mirrors, differential pairs, and/or resistor arrays in analog designs.

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AgO AnXplorer 2010.12 Analog Design Optimization Tool

AgO introduced AnXplorer 2010.12. The latest release features new feasibility analysis capability for rapidly identifying a feasible region for circuit design variables. AnXplorer 2010.12 increases productivity for analog IC designers. AnXplorer is a circuit optimization tool for analog and RF design. It uses an optimization approach that is based on either simulation or equations. The tool works with SPICE netlists and supports industry standard simulators — including Synopsys HSPICE, Cadence Spectre, Mentor Eldo and Legend Design Technology MSIM. AnXplorer runs on the Linux operating system.

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Mentor Graphics and Dongbu HiTek Technology Design Kits for Analog BCDMOS

Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.

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SynaptiCAD WaveFormer Pro, Timing Diagrammer Pro, DataSheet Pro v15

SynaptiCAD rolled out version 15 of WaveFormer Pro, Timing Diagrammer Pro, and DataSheet Pro. The Timing Diagram Editors and test bench generators are available on Linux, Solaris, and Windows. Perpetual licenses start at $1,725 in a node-locked configuration. Time-based licenses are also available. WaveViewer is a free waveform viewer capable of displaying results of analog and digital simulations, and waveforms acquired from test equipment. The GigaWave option can be added to any of the products to boost the performance for very large files.

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Titan Analog Layout Accelerator and Titan Analog Virtual Prototyper

Magma Design Automation introduced the Titan Analog Layout Accelerator (ALX) and the Titan Analog Virtual Prototyper (AVP). Titan ALX and Titan AVP accelerate the creation and optimization of new analog design layouts, and automate the reuse of existing analog layouts in new processes and technologies. Titan ALX automatically migrates an existing analog layout to a new target technology without any DRC violations while preserving analog design intent. Titan AVP creates fast and accurate device-level prototypes and captures layout-dependent proximity effects early in the circuit design phase. Titan ALX and Titan AVP will be in production release in June 2010.

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