Synopsys has added a Performance Checker capability to their next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol. The Performance Checker capability in the Synopsys Discovery VIP helps improve the productivity of engineering teams using the AMBA protocols to meet their SoC performance goals.
According to Mentor Graphics, their Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. The Questa Codelink with support for ARM Cortex A7, Cortex A15, other Cortex A-family, Cortex R-family, and Cortex M-family processors and Questa Verification IP with support for AMBA4 ACE are available now.
Carbon Design Systems announced a TLM-2.0 solution for the AMBA protocol. The solution enables modeling the AMBA protocols with SystemC TLM2-0. The TLM-2.0 for the AMBA protocol solution will execute in any SystemC environment and contains no runtime licensing. Engineers can create models representing AMBA intellectual property (IP) blocks at any level of abstraction. The TLM-2.0 for the AMBA protocol solution is available for free from Carbon’s IP Exchange.
Jasper Design Automation announced Intelligent Proof Kits for accelerated certification of advanced SoC interconnect protocols. Jasper Intelligent Proof Kits ship unencrypted with original source code to facilitate user customization and insights into the protocols themselves. Jasper is initially releasing Intelligent Proof Kits for AMBA 3 and AMBA 4. DFI, DDR and LPDDR versions will roll out a little later.
ARM unveiled the first phase of the new AMBA 4 specification. The AMBA specification is the de facto standard for system on-chip interconnects. The AMBA 4 increases functionality and efficiency for complex, media-rich on-chip communication. The AMBA 4 specification has been designed by and for the industry with contributions from 35 of the industry’s leading OEM, semiconductor, and EDA vendors.
Sonics Network for AMBA Protocol (SNAP) will offer SoC designers, free-of-charge, tools and IP for capturing and analyzing bus designs via its new online SNAP evaluation environment. The new product simplifies the evaluation process of Sonics IP, helps designers with their on-chip network designs, and eliminates the need for complicated licenses inherent in conventional IP evaluations.
The CoWare SBL-301 SystemC Bus Library for Platform Architect enables early configuration, exploration, and optimization of next-generation system-on-chip (SoC) architectures using AMBA technology-based virtual platforms in SystemC. The new CoWare SBL-301 SystemC Bus Library and architecture design solution featuring CoWare Platform Architect and AMBA designer ADR-301 is available for early customer evaluation now. Production release is expected in December 2009.