Tag Archives: Aldec

HiPer Simulation A/MS Features Tools from Tanner EDA, Aldec

Tanner EDA and Aldec teamed together on HiPer Simulation A/MS, which is an integrated co-simulation solution for analog and mixed-signal (A/MS) design. HiPer Simulation A/MS includes Tanner EDA’s T-Spice analog design capture and simulation tool, and Aldec’s Riviera-PRO mixed language digital simulator. The integrated solution helps both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform. HiPer Simulation A/MS is available on both Windows and Linux.

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Aldec ALINT 2010.06 with Phase-Based Linting Methodology

Aldec introduced ALINT 2010.06, which is a design rule checking software solution. ALINT 2010.06 features a phase-based linting (PBL) methodology that provides structured and prioritized phases for the analysis of HDL design issues. The design rule checking tool reduces the number of linting iterations and error messages at each phase. ALINT eliminates more design issues incrementally at each phase. Default phases may be modified or customized by engineers for adherence to corporate design policies or conducting targeted design rule checks. The latest release of ALINT is available now. The tool supports STARC, RMM, DO-254 and Aldec design rule plug-ins, which are sold separately.

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Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.

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Automatic Generation of Flexible Testbenches Webinar

Aldec is offering a webinar, Automatic Generation of Flexible Testbenches. The webcast will take place February 18, 2010. There will be two sessions. Session 1 will take from 3:00 pm to 4:00 pm (Central Europe Time Zone) and Session 2 will take place 11:00 am to 12:00 pm (Pacific Standard Time Zone). The online seminar will be presented by Mr. Jerry Long, Applications Engineer at EMA Design Automation.

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Aldec ALINT 2009.10 for Design Rule Checking

Aldec introduced ALINT 2009.10 Design Rule Checking application. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT is Design Rule Checking software for fast design closure. ALINT analyzes and detects issues early in the design and verification cycle, and checks HDL source code of complex ASIC, FPGA, and SOC designs. It detects such problems as poor coding styles, improper clock and reset management, simulation and synthesis problems, poor testability, and source code issues throughout the design flow.

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