Tag Archives: Accellera

2012 Design and Verification Conference Seeking Papers and Tutorials

The Design and Verification Conference (DVCon) has issued a call for paper and panel abstract submissions, and tutorial proposals. DVCon wants engineers to present their experiences, solutions and ideas. Paper proposals are due August 15, 2011, tutorial proposals are due September 13th, and panel proposals are due September 19th. DVCon will be held February 27-March 1 in San Jose, California. DVCon 2012 is sponsored by Accellera.

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Design and Verification Conference 2011

The Design and Verification Conference (DVCon) will take place Monday, February 28 through Thursday, March 3 at the DoubleTree Hotel in San Jose, California. Keynote and featured panels include: From Volume to Velocity, Making Great Products Great, and VM — Final Answer or Phone a Friend? The event is sponsored by Accellera, which is an industry consortium dedicated to the development and standardization of design and verification languages.

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Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.

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Design and Verification Conference 2010

DVCon (Design and Verification Conference) will take place Monday, February 22 through Thursday, February 25 at the DoubleTree Hotel in San Jose, California. The event is ideal for engineers that work on the design and verification of electronic systems. DVCon consists of technical program, panels, sessions and educational presentations. It is sponsored by Accellera.

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