Tag Archives: 40nm

SMIC-Synopsys Reference Flow 5.0 Extends 40nm Low Power Capabilities

SMIC-Synopsys Reference Flow 5.0

Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.

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SMIC 40nm Reference Flow Features Cadence Encounter Digital Technology

Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.

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Synopsys DesignWare Data Converter IP Solutions for 40nm Process

Synopsys introduced DesignWare data converter IP solutions for 40-nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications, and video designs requiring high-performance, ultra-low power consumption and very compact area. The DesignWare Sigma-Delta ADCs, Current Steering DACs, Video DACs, and General Purpose ADCs and DACs in the 40-nm process are expected to be available in Q1 2010. The DesignWare Data Converter IP solutions are currently available in leading foundries and advanced technology processes from 180-nm to 65-nm.

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