Cadence Design Systems introduced Virtuoso Advanced Node, which is a set of custom/analog capabilities designed for the advanced technology nodes of 20 nanometers and below. Virtuoso Advanced Node enables design teams to optimize designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.
Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.
Cadence Design Systems and Samsung Electronics teamed together on a 20-nanometer design methodology. Their 20nm digital design methodology features double patterning technology for joint customer deployment and internal test chips. The new design methodology enables design at 20 nanometers and future process nodes. It is ideal for mobile consumer electronics.
Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.
Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.
Synopsys introduced IC Compiler-Advanced Geometry, which is a new configuration of their IC Compiler physical design product. IC Compiler-Advanced Geometry is a DPT-compliant place-and-route solution that will provide designers moving to 20 nanometers with an advanced solution. Synopsys has successfully collaborated with foundry partners and major customers to validate that IC Compiler is 20nm-ready.