LDRA Announces MISRA C:2012 Seminars

LDRA announced the MISRA C:2012 seminars. The half-day events introduces the new features of the MISRA C:2012, highlighting how the revised standard enables developers to take advantage of more C features, while avoiding unsafe C constructs. Project managers, software engineers, system engineers, software technical leads, verification engineers, process engineers, engineering managers, academics, and regulators will benefit from the MISRA C:2012 seminars.

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Cadence Mixed-Signal Technology Summit 2013

Cadence Design Systems is holding their Mixed-Signal Summit next week. The event will give attendees the opportunity to learn from experts at Cadence and other leading companies about the latest mixed signal design methodologies, and new Cadence technologies such as support for System Verilog real number modeling based on the IEEE P1800 standard. The free day-long event will take place at its San Jose headquarters on October 10th.

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Synopsys Debuts Galaxy Implementation for TSMC 16nm FinFET Reference Flow

Synopsys introduced a comprehensive design implementation solution for TSMC’s 16-nanometer (nm) FinFET reference flow. The jointly developed reference flow is built on tool certification currently in TSMC’s V0.5 Design Rule Manual (DRM) and SPICE. The collaboration between the two companies has resulted in a comprehensive FinFET implementation flow that can be deployed for production use by mutual customers.

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Mentor FloEFD CFD Tool Features Monte-Carlo Radiation Modeling, Multicore Meshing

Mentor Graphics introduced a new verion of FloEFD concurrent computational fluid dynamics tool. The new FloEFD features Monte-Carlo radiation modeling for thermo-optical performance and multicore meshing of complex geometries that speeds simulation magnitude faster. The Mentor CFD tool with Monte-Carlo modeling and multicore meshing enhancements is available for now.

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Seminar: Acquiring and Analyzing Data from Sensors and In-Vehicle Networks

SAE International is offering a seminar titled: Acquiring and Analyzing Data from Sensors and In-Vehicle Networks. The SAE seminar will review the traditional approach of acquiring data directly from sensors and cover the newer approach of obtaining data from the in-vehicle network for automotive, heavy duty, off-road, and marine applications. The event will take place November 6-7, 2013 (8:30 am – 4:30 pm) in Troy, Michigan.

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Synopsys Debuts CODE V 10.6 Optical Design Software

Synopsys CODE V 10.6 Optical Design Software

Synopsys released version 10.6 of their CODE V Optical Design Software. CODE V is an optical engineering and design software solution that supports the optimization, analysis and tolerancing of image-forming optical systems and free-space photonic devices. CODE v10.6 enables faster development of new and emerging optical technologies that improves performance CODE V version 10.6 is available now.

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Real Intent Releases New Version of Ascent X-Verification System Tool

Real Intent Ascent X-Verification System (XV) tool

Real Intent introduced the latest version of Ascent X-Verification System (XV) tool for early functional analysis of digital designs. The new version features enhancements for initialization analysis, and the detection and management of unknown logic values (X’s). The latest version of Ascent XV is available now for download.

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3D Solid Modeling and Analysis Webinar

Tanner EDA will host a webinar about 3D solid modeling and analysis. The webcast will demonstrate a 3D solid modeling and analysis capability that may be used for the design of MEMS and integrated MEMS-IC devices, their associated electronics and packaging in commercial MEMS systems. The online seminar will take place Tuesday, September 24th, 2013 from 8:30am to 9:30am Pacific time.

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Cadence Design Systems Debuts Secure Digital 4.0 Host Controller IP Core

Cadence Design Systems introduced the Secure Digital (SD) 4.0 Host Controller Intellectual Property core. The IP core helps designers achieve the maximum memory card access performance of up to 312MB/s (three times the performance of the previous specification). The Secure Digital 4.0 Host Controller IP core is available now.

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Cadence Develops First Verification IP for HDMI 2.0

Cadence Design Systems has developed the industry’s first verification IP that supports the new HDMI 2.0 specification. The HDMI 2.0 VIP enables a small verification team to deliver reliable results within very tight schedule constraints. By reducing the effort required to develop a verification solution, engineers can focus on other tasks crucial to project completion.

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