Category Archives: Test Solution

test sloutions, qa, test, measure

ProPlus Design Solutions Debuts 9812D Wafer-level Noise Measurement System

ProPlus Design Solutions 9812D wafer-level, 1/f noise measurement system

ProPlus Design Solutions introduced the 9812D wafer-level, 1/f noise measurement system. The 9812D features highly accurate measurement, a frequency range that exceeds 10 Megahertz (MHz), built-in dynamic signal analyzer (DSA), and multi-threaded processing. ProPlus Design Systems is accepting orders now for 9812D. The products will start shipping in March.

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Keithley Instruments Debuts Model 2110 Dual-Display Digital Multimeter

Keithley Model 2110 Dual-Display Digital Multimeter front view

Keithley Instruments launched the Model 2110 5½-digit Dual-Display Digital Multimeter. The rugged DMM features 15 measurement functions, seven math functions and dual-line display capability, which allows it to display two different measurements concurrently. The Model 2110 is ideal for production, R&D, and test engineers, scientists, and students making a wide variety of measurements in portable, bench, and system applications.

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National Instruments Shares Automated Test Outlook for 2013

National Instruments published their 2013 Automated Test Outlook. The report highlights the latest test and measurement technologies and methodologies. The research examines trends affecting industries such as aerospace and defense, automotive, consumer electronics, semiconductor, telecommunications and transportation.

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PLS Universal Debug Engine 4.0 Supports Multicore Targets

PLS Programmierbare Logik & Systeme Universal Debug Engine (UDE) 4.0

PLS Programmierbare Logik & Systeme released version four of their Universal Debug Engine (UDE). UDE 4.0 features improved debug capabilities for multicore targets, optimized visualization options during system test and dedicated support for the latest 32-bit multicore System-On-Chips (SOCs). UDE 4.0 now supports microcontrollers (MCUs) for the Infineon AURIX family, Freescale Qorivva MPC57XX family, and STMicroelectronics SPC57x family.

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XJTAG 3.0 Boundary Scan Development System

XJTAG 3.0 boundary scan development system

XJTAG released the latest version of their boundary scan development system. Engineers can intuitively learn how to use XJTAG 3.0 without attending lengthy and expensive training courses. The new XJTAG Development System is now available on a 30-day free trial.

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Coverity Launches Development Testing Platform v6.5

Coverity launched version 6.5 of their Development Testing Platform, which is an integrated suite of software testing technologies for identifying and remediating critical quality and security issues during development. The latest version features Coverity Test Advisor for change impact analysis and unit testing on high risk code, including changed code and code impacted by a change, alerting developers of code not covered by unit tests. Coverity Development Testing Platform 6.5 is available now.

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EVE Debuts e-zTest MIPI CSI-2 and MIPI DSI Validation Platforms

EVE introduced the e-zTest MIPI CSI-2 and e-zTest MIPI DSI validation platforms. The new application-specific debug solutions support the Mobile Industry Processor Interface (MIPI) Alliance wireless standards for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI). The two new wireless system-on-chip (SoC) validation platforms are the first commercial synthesizable virtual components for SoC emulation that meet MIPI standards. The EVE platforms are available now.

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Atollic Introduces TrueSTUDIO for ARM v3.2

Atollic TrueSTUDIO for ARM v3.2

Atollic introduced TrueSTUDIO for ARM v3.2. The integrated development environment for embedded microcontroller designs now offers RTOS-aware debug support for real-time operating systems like FreeRTOS, OpenRTOS, ThreadX and embOS. The ARM development tool is an integrated C/C++ solution with features for multicore debugging, improved code quality, team collaboration and increased developer efficiency. Atollic TrueSTUDIO v3.2 helps engineers to quickly develop embedded systems with higher quality and at lower cost.

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Avery Design Systems Introduces SCSI-Xactor Verification IP for PCIe-based SSD

Avery Design Systems recently introduced their SCSI-Xactor verification IP. SCSI-Xactor targets SCSI Express for high performance PCIe-based SSDs. Avery’s verification IP is a complete solution for SCSI Express core and system design. SCSI-Xactor helps design and verification engineers to quickly and extensively test the functionality of SCSI Express controller-based designs.

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ASSET InterTech Publishes IJTAG Tutorial on New Standard for Chip Validation and Characterization

ASSET InterTech IJTAG Tutorial

ASSET InterTech has published an introductory tutorial on IJTAG. The tutorial explains how the new IEEE P1687 Internal JTAG (IJTAG) standard simplifies and automates the way chip designers manage embedded instruments that perform chip validation and characterization. The article describes the on-chip IJTAG architecture and the two languages defined by the standard, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the connections among embedded on-chip instruments and PDL is an extension of the Tcl (Tool Command Language) for developing validation, test and debug vectors for execution by IJTAG instruments.

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