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	<title>EDA Blog &#187; Test Solution</title>
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	<link>http://edablog.com</link>
	<description>Electronic Design Automation Software, Hardware, and Components</description>
	<lastBuildDate>Thu, 24 May 2012 04:01:44 +0000</lastBuildDate>
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		<title>Carbon Design Systems and Cadence Design Systems Team on Performance Analysis Kit</title>
		<link>http://edablog.com/2012/05/24/cpak-coremark/</link>
		<comments>http://edablog.com/2012/05/24/cpak-coremark/#comments</comments>
		<pubDate>Thu, 24 May 2012 04:01:44 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[ARM]]></category>
		<category><![CDATA[Cadence Design Systems]]></category>
		<category><![CDATA[Carbon Design Systems]]></category>
		<category><![CDATA[CoreMark]]></category>
		<category><![CDATA[Cortex-A9]]></category>
		<category><![CDATA[CPAK]]></category>
		<category><![CDATA[DDR3]]></category>
		<category><![CDATA[EEMBC]]></category>
		<category><![CDATA[IP]]></category>
		<category><![CDATA[IP Exchange]]></category>
		<category><![CDATA[Memory Controller]]></category>
		<category><![CDATA[MPCore]]></category>
		<category><![CDATA[Performance Analysis Kit]]></category>
		<category><![CDATA[processor]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=8011</guid>
		<description><![CDATA[Carbon Design Systems and Cadence Design Systems announced the availability of a Carbon Performance Analysis Kit. The CPAK accelerates the intellectual property (IP) benchmark process. The Carbon/Cadence CPAK is available now from Carbon&#8217;s IP Exchange web portal. Ported CoreMark benchmarking software is available from coremark.org. Read more: Carbon Design Systems and Cadence Design Systems Team [...]]]></description>
			<content:encoded><![CDATA[<p>Carbon Design Systems and Cadence Design Systems announced the availability of a Carbon Performance Analysis Kit. The CPAK accelerates the intellectual property (IP) benchmark process. The Carbon/Cadence CPAK is available now from Carbon&#8217;s IP Exchange web portal. Ported CoreMark benchmarking software is available from coremark.org.</p>
<p><p>Read more: <a href="http://edablog.com/2012/05/24/cpak-coremark/">Carbon Design Systems and Cadence Design Systems Team on Performance Analysis Kit</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/05/24/cpak-coremark/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/05/24/cpak-coremark/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Corelis Introduces ScanExpress Boundary-Scan Tool Suite v7.7</title>
		<link>http://edablog.com/2012/05/23/jtag-test/</link>
		<comments>http://edablog.com/2012/05/23/jtag-test/#comments</comments>
		<pubDate>Wed, 23 May 2012 15:46:31 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[Boundary Scan]]></category>
		<category><![CDATA[Corelis]]></category>
		<category><![CDATA[Embedded Test]]></category>
		<category><![CDATA[JTAG]]></category>
		<category><![CDATA[Tool Suite]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=8000</guid>
		<description><![CDATA[Corelis launched version 7.7 of their ScanExpress Boundary-Scan Tool Suite. The latest version of the tool suite features improved constraints handling, support for multi-core devices, and new JTAG Embedded Test support for additional Freescale and Texas Instruments processors. ScanExpress Boundary-Scan Tool Suite, version 7.7 is available now to customers with a valid maintenance contract. Read [...]]]></description>
			<content:encoded><![CDATA[<p>Corelis launched version 7.7 of their ScanExpress Boundary-Scan Tool Suite. The latest version of the tool suite features improved constraints handling, support for multi-core devices, and new JTAG Embedded Test support for additional Freescale and Texas Instruments processors. ScanExpress Boundary-Scan Tool Suite, version 7.7 is available now to customers with a valid maintenance contract.</p>
<p><p>Read more: <a href="http://edablog.com/2012/05/23/jtag-test/">Corelis Introduces ScanExpress Boundary-Scan Tool Suite v7.7</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/05/23/jtag-test/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/05/23/jtag-test/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>EVE Introduces e-zTest 10GbE Validation Platform for ZeBu</title>
		<link>http://edablog.com/2012/05/17/10-gigabit-zero-bugs/</link>
		<comments>http://edablog.com/2012/05/17/10-gigabit-zero-bugs/#comments</comments>
		<pubDate>Thu, 17 May 2012 16:33:41 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Networking]]></category>
		<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[10-Gigabit]]></category>
		<category><![CDATA[10GbE]]></category>
		<category><![CDATA[debug]]></category>
		<category><![CDATA[e-zTest]]></category>
		<category><![CDATA[Ethernet]]></category>
		<category><![CDATA[EVE]]></category>
		<category><![CDATA[validation]]></category>
		<category><![CDATA[ZeBu]]></category>
		<category><![CDATA[Zero Bugs]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7989</guid>
		<description><![CDATA[EVE introduced e-zTest 10GbE, which is a 10-Gigabit Ethernet validation platform for their ZeBu (Zero Bugs) family of system-on-chip (SoC) hardware-assisted verification platforms. The e-zTest 10GbE software is a transaction-based environment for high-speed validation of 10GbE functions in network routers, switches and controllers, and SoC application specific integrated circuits (ASICs) containing 10GbE ports. Read more: [...]]]></description>
			<content:encoded><![CDATA[<p>EVE introduced e-zTest 10GbE, which is a 10-Gigabit Ethernet validation platform for their ZeBu (Zero Bugs) family of system-on-chip (SoC) hardware-assisted verification platforms. The e-zTest 10GbE software is a transaction-based environment for high-speed validation of 10GbE functions in network routers, switches and controllers, and SoC application specific integrated circuits (ASICs) containing 10GbE ports.</p>
<p><p>Read more: <a href="http://edablog.com/2012/05/17/10-gigabit-zero-bugs/">EVE Introduces e-zTest 10GbE Validation Platform for ZeBu</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/05/17/10-gigabit-zero-bugs/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/05/17/10-gigabit-zero-bugs/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing</title>
		<link>http://edablog.com/2012/04/30/triplecheck-ip-verification/</link>
		<comments>http://edablog.com/2012/04/30/triplecheck-ip-verification/#comments</comments>
		<pubDate>Mon, 30 Apr 2012 16:19:40 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[Cadence Design Systems]]></category>
		<category><![CDATA[Compliance Testing]]></category>
		<category><![CDATA[IP]]></category>
		<category><![CDATA[IP Validator]]></category>
		<category><![CDATA[IP Verification]]></category>
		<category><![CDATA[simulator]]></category>
		<category><![CDATA[SystemVerilog]]></category>
		<category><![CDATA[test]]></category>
		<category><![CDATA[TripleCheck]]></category>
		<category><![CDATA[Verification IP]]></category>
		<category><![CDATA[VIP Catalog]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7924</guid>
		<description><![CDATA[Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://edablog.com/primages/2012/Cadence-TripleCheck.gif" width="250" height="336" alt="Cadence TripleCheck IP Validator for Faster IP Compliance Testing" border="0" /></p>
<p>Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/30/triplecheck-ip-verification/">Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/30/triplecheck-ip-verification/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/30/triplecheck-ip-verification/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Mentor Graphics Veloce2 Emulation Platform Features VirtuaLAB Capabilities</title>
		<link>http://edablog.com/2012/04/25/crystal2-verification/</link>
		<comments>http://edablog.com/2012/04/25/crystal2-verification/#comments</comments>
		<pubDate>Wed, 25 Apr 2012 16:41:01 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[Crystal2]]></category>
		<category><![CDATA[Emulation]]></category>
		<category><![CDATA[Mentor Graphics]]></category>
		<category><![CDATA[Veloce2]]></category>
		<category><![CDATA[verification]]></category>
		<category><![CDATA[VirtuaLAB]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7912</guid>
		<description><![CDATA[Mentor Graphics introduced the Veloce2 emulation platform for the verification of electronic system and Systems on Chip (SoC) designs. Mentor also announced Veloce VirtuaLAB, which gives verification engineers access to easy-to-use, software-based peripherals, connected to the Veloce platform. Veloce2 helps software and hardware engineers verify the embedded software and SoC components of high-end CPUs, network [...]]]></description>
			<content:encoded><![CDATA[<p>Mentor Graphics introduced the Veloce2 emulation platform for the verification of electronic system and Systems on Chip (SoC) designs. Mentor also announced Veloce VirtuaLAB, which gives verification engineers access to easy-to-use, software-based peripherals, connected to the Veloce platform. Veloce2 helps software and hardware engineers verify the embedded software and SoC components of high-end CPUs, network switches/routers, digital set-top boxes, tablet PCs, netbooks, smartphones, digital cameras and other electronic products. The Veloce2 platform and Veloce VirtuaLAB are available now.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/25/crystal2-verification/">Mentor Graphics Veloce2 Emulation Platform Features VirtuaLAB Capabilities</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/25/crystal2-verification/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/25/crystal2-verification/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Mentor Graphics Questa Verification IP Supports MIPI Alliance Specifications</title>
		<link>http://edablog.com/2012/04/20/vip-ovm-uvm/</link>
		<comments>http://edablog.com/2012/04/20/vip-ovm-uvm/#comments</comments>
		<pubDate>Fri, 20 Apr 2012 15:39:01 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[Library]]></category>
		<category><![CDATA[Mentor Graphics]]></category>
		<category><![CDATA[MIPI]]></category>
		<category><![CDATA[MIPI Alliance]]></category>
		<category><![CDATA[OVM]]></category>
		<category><![CDATA[Protocol]]></category>
		<category><![CDATA[Questa Verification IP]]></category>
		<category><![CDATA[SystemVerilog]]></category>
		<category><![CDATA[test bench]]></category>
		<category><![CDATA[UVM]]></category>
		<category><![CDATA[Verification IP]]></category>
		<category><![CDATA[VIP]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7891</guid>
		<description><![CDATA[Mentor Graphics&#8217; Questa Verification IP (VIP) now supports several MIPI Alliance specifications. This includes CSI, DSI and the recently announced LLI. Questa VIP is a comprehensive solution for SystemVerilog OVM and UVM test benches. Questa VIP support for MIPI protocols is available now for select customers. Read more: Mentor Graphics Questa Verification IP Supports MIPI [...]]]></description>
			<content:encoded><![CDATA[<p>Mentor Graphics&#8217; Questa Verification IP (VIP) now supports several MIPI Alliance specifications. This includes CSI, DSI and the recently announced LLI. Questa VIP is a comprehensive solution for SystemVerilog OVM and UVM test benches. Questa VIP support for MIPI protocols is available now for select customers.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/20/vip-ovm-uvm/">Mentor Graphics Questa Verification IP Supports MIPI Alliance Specifications</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/20/vip-ovm-uvm/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/20/vip-ovm-uvm/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>SynaptiCAD V2V Translators Feature Verilog 2001 Support, Graphical Debugger</title>
		<link>http://edablog.com/2012/04/19/vhdl-verilog-debugging/</link>
		<comments>http://edablog.com/2012/04/19/vhdl-verilog-debugging/#comments</comments>
		<pubDate>Thu, 19 Apr 2012 16:29:48 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[BugHunter Pro]]></category>
		<category><![CDATA[Debugging]]></category>
		<category><![CDATA[Graphical Debugger]]></category>
		<category><![CDATA[SynaptiCAD]]></category>
		<category><![CDATA[testing]]></category>
		<category><![CDATA[V2V]]></category>
		<category><![CDATA[V2V Translators]]></category>
		<category><![CDATA[Verilog]]></category>
		<category><![CDATA[VHDL]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7885</guid>
		<description><![CDATA[SynaptiCAD rolled out a new version of their V2V translator software. The SynaptiCAD V2V tools translate between VHDL and Verilog source code that supports Verilog 2001 code constructs. SynaptiCAD also announced that their BugHunter Pro can now be used as a graphical debugging environment for translating and testing the new models. Read more: SynaptiCAD V2V [...]]]></description>
			<content:encoded><![CDATA[<p>SynaptiCAD rolled out a new version of their V2V translator software. The SynaptiCAD V2V tools translate between VHDL and Verilog source code that supports Verilog 2001 code constructs. SynaptiCAD also announced that their BugHunter Pro can now be used as a graphical debugging environment for translating and testing the new models.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/19/vhdl-verilog-debugging/">SynaptiCAD V2V Translators Feature Verilog 2001 Support, Graphical Debugger</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/19/vhdl-verilog-debugging/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/19/vhdl-verilog-debugging/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>PragmaDev Releases Version 4.3 of Real Time Developer Studio</title>
		<link>http://edablog.com/2012/04/18/modeling-rtds-v4-3/</link>
		<comments>http://edablog.com/2012/04/18/modeling-rtds-v4-3/#comments</comments>
		<pubDate>Wed, 18 Apr 2012 15:52:34 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Models, Simulations]]></category>
		<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[Developer Studio]]></category>
		<category><![CDATA[development tool]]></category>
		<category><![CDATA[embedded]]></category>
		<category><![CDATA[Model Driven]]></category>
		<category><![CDATA[modeling]]></category>
		<category><![CDATA[PragmaDev]]></category>
		<category><![CDATA[real-time]]></category>
		<category><![CDATA[requirements]]></category>
		<category><![CDATA[RTDS]]></category>
		<category><![CDATA[test cases]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7864</guid>
		<description><![CDATA[PragmaDev rolled out version 4.3 of the Real Time Developer Studio. RTDS v4.3 includes 15 new features. According to PragmaDev, RTDS is the most complete model driven development and testing tool dedicated to real time and embedded applications. PragmaDev RTDS offers three levels of modeling and testing: informal, semi-formal, and fully formal. Read more: PragmaDev [...]]]></description>
			<content:encoded><![CDATA[<div align="center"><img src="http://edablog.com/primages/2012/RTDS-TTCN-3.gif" width="344" height="237" alt="PragmaDev Real Time Developer Studio, version 4.3" border="0" /></div>
<p>PragmaDev rolled out version 4.3 of the Real Time Developer Studio. RTDS v4.3 includes 15 new features. According to PragmaDev, RTDS is the most complete model driven development and testing tool dedicated to real time and embedded applications. PragmaDev RTDS offers three levels of modeling and testing: informal, semi-formal, and fully formal.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/18/modeling-rtds-v4-3/">PragmaDev Releases Version 4.3 of Real Time Developer Studio</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/18/modeling-rtds-v4-3/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/18/modeling-rtds-v4-3/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>ASSET InterTech Debuts Board Bring-up Solution for Intel Haswell Microarchitecture</title>
		<link>http://edablog.com/2012/04/12/scanworks-intel-haswell/</link>
		<comments>http://edablog.com/2012/04/12/scanworks-intel-haswell/#comments</comments>
		<pubDate>Thu, 12 Apr 2012 18:21:25 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[ASSET InterTech]]></category>
		<category><![CDATA[board bring-up]]></category>
		<category><![CDATA[debug]]></category>
		<category><![CDATA[Designs]]></category>
		<category><![CDATA[embedded instruments]]></category>
		<category><![CDATA[Haswell]]></category>
		<category><![CDATA[Intel]]></category>
		<category><![CDATA[microarchitecture]]></category>
		<category><![CDATA[ScanWorks]]></category>
		<category><![CDATA[test]]></category>
		<category><![CDATA[testing]]></category>
		<category><![CDATA[validate]]></category>
		<category><![CDATA[verification]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7860</guid>
		<description><![CDATA[ASSET InterTech announced new tools to structurally verify, functionally test, analyze performance margins and debug boards based on the Intel microarchitecture codenamed Haswell. ScanWorks board bring-up will be available in the second quarter of this year. Pricing for a base level ScanWorks platform for embedded instruments starts at $12,000. Read more: ASSET InterTech Debuts Board [...]]]></description>
			<content:encoded><![CDATA[<p>ASSET InterTech announced new tools to structurally verify, functionally test, analyze performance margins and debug boards based on the Intel microarchitecture codenamed Haswell. ScanWorks board bring-up will be available in the second quarter of this year. Pricing for a base level ScanWorks platform for embedded instruments starts at $12,000.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/12/scanworks-intel-haswell/">ASSET InterTech Debuts Board Bring-up Solution for Intel Haswell Microarchitecture</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/12/scanworks-intel-haswell/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/12/scanworks-intel-haswell/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>Rigol Technologies Introduces DSA815 Spectrum Analyzer</title>
		<link>http://edablog.com/2012/04/09/rf-wireless-testing-if/</link>
		<comments>http://edablog.com/2012/04/09/rf-wireless-testing-if/#comments</comments>
		<pubDate>Mon, 09 Apr 2012 19:03:20 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Test Solution]]></category>
		<category><![CDATA[Digital]]></category>
		<category><![CDATA[DSA815]]></category>
		<category><![CDATA[IF technology]]></category>
		<category><![CDATA[RF]]></category>
		<category><![CDATA[Rigol Technologies]]></category>
		<category><![CDATA[spectrum analyzer]]></category>
		<category><![CDATA[testing]]></category>
		<category><![CDATA[Wireless]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7846</guid>
		<description><![CDATA[Rigol Technologies launched their DSA815 spectrum analyzer. The DSA815 features all-digital IF technology, highly precise amplitude readings, frequency range of 9kHz to 1.5 GHz, compact design and easy-to-use interface. The DSA815 is easy to use and highly reliable. The Rigol DSA815 spectrum analyzer is available now. Prices start at $1,295. It is ideal for demanding [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://edablog.com/primages/2012/Rigol-DSA815-Spectrum-Analyzer.jpg" width="400" height="200" alt="Rigol Technologies DSA815 spectrum analyzer " border="0" /></p>
<p>Rigol Technologies launched their DSA815 spectrum analyzer. The DSA815 features all-digital IF technology, highly precise amplitude readings, frequency range of 9kHz to 1.5 GHz, compact design and easy-to-use interface. The DSA815 is easy to use and highly reliable. The Rigol DSA815 spectrum analyzer is available now. Prices start at $1,295. It is ideal for demanding benchtop or field applications in RF and wireless testing and production.</p>
<p><p>Read more: <a href="http://edablog.com/2012/04/09/rf-wireless-testing-if/">Rigol Technologies Introduces DSA815 Spectrum Analyzer</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/04/09/rf-wireless-testing-if/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/04/09/rf-wireless-testing-if/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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