EDA Blog » Research

Non-Intrusive Board Bring-Up: Software Tools Ensure Fast Prototype Bring-Up White Paper

Ken Cheung — Wed, 25 Jan 2012 16:44:52 +0000

ASSET InterTech recently published a white paper titled: Non-Intrusive Board Bring-Up: Software Tools Ensure Fast Prototype Bring-Up. The technical paper explains how non-intrusive software tools can bring up prototype circuit boards faster than legacy hardware-oriented tools like oscilloscopes and logic analyzers. The white paper reviews best practices for board bring-up and describes the benefits of integrating non-intrusive tools based on embedded instruments into an organization’s board bring-up framework.

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New Cadence Book: Advanced Verification Topics

Ken Cheung — Thu, 19 Jan 2012 15:43:01 +0000

Cadence Design Systems published a new book: Advanced Verification Topics. The 229-page book describes the latest techniques and methodologies for verifying today’s most complex IP and systems on chips (SoCs). It discusses topics like metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM. The Cadence book is ideal for aid verification engineers. It builds on a prior Cadence book, A Practical Guide to Adopting the Universal Verification Methodology (UVM).

White Paper: An Electrical-Thermal MMIC Design Flow

Ken Cheung — Tue, 13 Dec 2011 17:08:36 +0000

AWR recently published a white paper about the benefits of co-simulation. The title of the white paper is: An Electrical-Thermal MMIC Design Flow. The technical paper uses an actual design example to discuss the effectiveness of co-simulation between AWR’s Microwave Office high-frequency design software and CapeSym’s SYMMIC thermal analysis tool. An X-band RF power amplifier/low-noise amplifier MMIC for a transceiver application was designed in Microwave Office software and thermal coupling and other issues between the two circuits on the single die were quickly remedied with SYMMIC to produce optimum results.

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Application Note: Linking RF Design and Test through AWR Software and LabVIEW

Ken Cheung — Fri, 07 Oct 2011 18:38:43 +0000

AWR has a new application note that explains how EDA tool integration benefits designers of circuits for 3G and 4G wireless systems. The app note describes the benefits of using AWR’s Microwave Office and Visual System Simulator (VSS) high-frequency design software with National Instruments’ LabVIEW signal processing software and virtual instruments. The title of the paper is Using LabVIEW in the AWR Design Environment To Design Complex Circuits for Wireless Applications.

Application Note: High-Speed Serial Backplane – SERDES Design Example

Ken Cheung — Wed, 05 Oct 2011 19:00:57 +0000

AWR published an application note, High-Speed Serial Backplane – SERDES Design Example. The paper discusses the advantages of AWR Connected for Anritsu VectorStar for designing high-speed serial backplanes. AWR’s Microwave Office software is resident in the Anritsu VectorStar VNA. High-frequency design tools resident on a Vector Network Analyzer (VNA) provides a streamlined work flow that eliminates the time required to transfer measured data to a simulator running on a separate PC or workstation.

Mastering Power Modules: The Advantages Over Discrete Solutions Article

Ken Cheung — Fri, 30 Sep 2011 16:03:12 +0000

Vincotech has published an article titled, Mastering Power Modules: The advantages over discrete solutions. According to Vincotech, power modules have become the most convenient way of building a cost effective power supply system. Everything is optimized within the constraints of the particular module manufacturer. The designer can rest assured that the module will do everything electrically and mechanically that is specified, is guaranteed to work to tight specifications such as EMI, efficiency, load cycling and reliability and it is virtually off-the-shelf meaning that the all-important time to market pressure is minimized.

Synthesizing and Optimizing a Hairpin Bandpass Filter with AWR Tools App Note

Ken Cheung — Thu, 25 Aug 2011 18:49:42 +0000

AWR published a new application note about the synthesis and design of complex filters. The app note uses a hairpin bandpass filter to illustrate how AWR’s iFilter synthesis software in conjunction with Microwave Office high-frequency design software and AXIEM 3D planar electromagnetic (EM) solver can help designers create filters that conform to specific manufacturing constraints and costs. The title of the paper is Synthesizing and Optimizing a Hairpin Bandpass Filter with AWR Tools.

Piezo Technology in Materials Testing Technote

Ken Cheung — Thu, 30 Jun 2011 18:51:26 +0000

PI (Physik Instrumente) published an interesting technote about using scanning probe microscopy with piezo stages and capacitive nanometrology sensors to improve nano-indentation and materials testing systems. The NanoTest from Micro Materials is ideal for use with a wide range of materials because it can apply forces of between 30 nN and 500 mN depending on the operating mode, and it can measure penetration depths of between 0.1 nm and 50 ìm. The task is carried out by a high-resolution capacitive sensor, the PISeca sensor from PI.

Micro- and Nanopatterning of Inorganic and Polymeric Substrates by Indentation Lithography

Ken Cheung — Fri, 22 Apr 2011 14:16:28 +0000

The Whitesides Group at Harvard University and CSM Instruments published an nanotech article on complex 3D-nano patterns with Indentation Lithography (IndL) and piezo technology. The paper describes the use of a nanoindenter, equipped with a diamond tip, to form patterns of indentations on planar substrates (epoxy, silicon, and SiO2). The indentations have the form of pits and furrows, whose cross-sectional profiles are determined by the shapes of the diamond indenters, and whose dimensions are determined by the applied load and hardness of the substrate.

Imec Creates Optical I/O Industrial Affiliation Program

Ken Cheung — Wed, 26 Jan 2011 15:21:05 +0000

Imec is creating a new industrial research program on high-bandwidth optical input/output (I/O). The goal of the new program is to explore the use of optical solutions for realizing high-bandwidth I/O between CMOS chips. The affiliation program is a part of imec’s research platform on deep-submicron CMOS scaling. In close collaboration with imec’s industrial partners, the optical I/O program will develop a silicon-photonics solution for addressing the upcoming scaling challenges in interconnecting CMOS chips.