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'Research' Category Archive

Imec and Synopsys to Accelerate 3D Stacked IC Development

Posted by Ken Cheung in Research on Tuesday, March 9, 2010

Synopsys and imec will collaborate to accelerate the development of 3D stacked IC technologies. Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools will be used for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs). The collaboration will accelerate the development of 3D stacked IC technologies.

AMBA 4 Open Specifications, Phase One

Posted by Ken Cheung in Research on Tuesday, March 9, 2010

ARM unveiled the first phase of the new AMBA 4 specification. The AMBA specification is the de facto standard for system on-chip interconnects. The AMBA 4 increases functionality and efficiency for complex, media-rich on-chip communication. The AMBA 4 specification has been designed by and for the industry with contributions from 35 of the industry’s leading [...]

Distinguishing Between Real and Imitation In-Memory Database Systems

Posted by Ken Cheung in Research on Friday, February 12, 2010

McObject recently published a white paper, “Will the Real IMDS Please Stand Up?” The technical explains how to tell the difference between real and imitation in-memory database systems, and explains why it matters. The free report helps developers determine if they will obtain the IMDS benefits of fast performance and superior database efficiency from specific [...]

AWR Hardware in the Loop White Paper

Posted by Ken Cheung in Research on Thursday, February 11, 2010

When simulating a complete subsystem (such as a wireless communication device or radar receiver), the quality of measurement data becomes essential to ensure that the finished product meets or exceeds the demands the system will encounter in service. The measurement data can be used to make changes to the system early in the design process, [...]

Holst Centre, imec, TNO Team on Dual Gate Organic TFT RFID Circuit

Posted by Ken Cheung in Research on Wednesday, February 10, 2010

Holst Centre, imec, and TNO teamed on a dual-gate-based organic RFID chip with record data rate and lowest reported operating voltage. The advantages of dual gate transistors in circuit speed and robustness have been used in a complex organic-electronic circuit. Further and ongoing work will demonstrate the viability of the technology towards industrial uptake.

Electronic Design Automation Revenue Declines by 3.8% in Q3 2009

Posted by Ken Cheung in Research on Friday, January 15, 2010

According to the EDA Consortium (EDAC) Market Statistics Service (MSS), the Electronic Design Automation (EDA) industry revenue for Q3 2009 is $1,167.9 million, a 3.8% sequential increase from Q2. On a Q3/Q3 basis, EDA industry revenue declined 7.2%, compared to $1,258.6 million in Q3 2008. The four-quarter moving average declined 13.1%. Companies that were tracked [...]

50 kbits/s Organic Transponder Circuit

Posted by Ken Cheung in Research on Thursday, December 10, 2009

Imec and TNO showcased the first organic transponder circuit with a bit rate of 50 kbits/s. The bit rate approaches the requirements for the Electronic Product Coding (EPC) standards. The Electronic Product Code has been developed for wireless identification in high-volume logistics applications like retail. It is widely used already today e.g. on pallet level [...]

Imec Double Heterostructure FET for GaN-on-Si Power Switching Devices

Posted by Ken Cheung in Research on Tuesday, December 8, 2009

Imec announced an innovative, simple, and robust GaN-on-Si double heterostructure FET (field effect transistor) architecture for GaN-on-Si power switching devices. The architecture meets the normally off requirements of power switching circuits and is characterized by low leakage and high breakdown voltage, both essential parameters to reduce the power loss of high-power switching applications.

Intel Westmere 32nm Layout and Design for Manufacturability Analysis

Posted by Ken Cheung in Research on Thursday, December 3, 2009

Chipworks announced their Design for Manufacturability (DFM) analysis of Intel’s 32 nm Clarkdale/Westmere microprocessor from the Core i5 660. The analysis combines a standard reverse engineering report with the ICWorks Surveyor format. ICWorks Surveyor is a software tool that allows the engineer to navigate thousands of images stitched together into a massive floor-plan across all [...]

IMEC Microchip with Microscopic Nail Structures

Posted by Ken Cheung in Research on Monday, November 9, 2009

IMEC announced a microchip with microscopic nail structures that enable close communication between the electronics and biological cells. The new chip is a mass-producible, easy-to-use tool in electrophysiology research (such as fundamental research on the functioning and dysfunctioning of the brain). Each micronail structure serves as a close contact-point for one cell, and contains an [...]

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